Dual layer surface gate JFET having enhanced gate-channel breakdown voltage

A method of manufacturing a semiconductor device comprising the steps of:

• (a) providing a semiconductor substrate of a first conductivity type having a first surface;
• (b) forming first and second semiconductor regions of a second conductivity type, opposite to said first conductivity type, into first and second spaced-apart surface portions of said substrate, respectively;
• (c) forming a third, channel, semiconductor region of said second conductivity type, into a portion of said substrate beneath a third surface portion of said substrate, so as to bridge said first and second semiconductor regions;
• and
• (d) forming, in said third surface portion of said substrate, a surface gate region of said first conductivity type, laterally between said first and second regions and contiguous with said channel region, said surface gate region including a fifth semiconductor region of a first impurity concentration extending from said third surface portion of said substrate to a sixth semiconductor region of a second impurity concentration, lower than said first impurity concentration, said sixth region being contiguous with said channel region, and such that the entirety of said laterally extending sixth region is spaced apart from said first surface of said substrate.