System for dynamically providing predicted high/slow speed accessing memory to a processing unit based on instructions

A method for dynamically providing selective high speed memory addressing in a system having a processing unit and a random access memory connected to supply instructions to the processing unit, the random access memory being operable in a high speed mode for predetermined sequences of addresses and otherwise operable in a low speed mode, the method comprising the steps of:

• providing instructions from the random access memory to the processing unit;
• predicting from the provided instructions if a subsequent memory access is to an address accessible in the high speed mode;
• and
• addressing said random access memory in the high speed mode in response to a prediction and in the low speed mode otherwise.

A system for dynamically providing selective high speed memory addressing, the system comprising;

• a processing unit;
• a random access memory connected to supply instructions to said processing unit in response to memory accesses from said processing unit, said random access memory being operable in a high speed mode for predetermined sequences of addresses and otherwise operable in a low speed mode;
• predicting means coupled to receive instructions supplied to said processing unit for providing a first signal in response to received instructions if the next memory access is to an address that accessible in the high speed mode;
• and
• mode selection means for accessing said random access memory in the high speed mode in response to the first signal and in the low speed mode otherwise.