Single event upset hardening CMOS memory circuit

Abstract

A CMOS storage cell includes an n-channel storage circuit which has cross coupled n-channel storage transistors and a p-channel storage circuit including cross coupled p-channel storage transistors. Each of the n-channel storage transistors has an n-channel load transistor and each of the p-channel storage transistors has a p-channel load transistor. The n-channel load transistors are coupled to be controlled by the p-channel storage circuit and the p-channel load transistors are coupled to be controlled by the n-channel storage circuit. The n-channel load transistors are designed to carry less current than the p-channel storage transistors and the p-channel load transistors are designed to carry less current than the n-channel storage transistors. The storage cell can be used for a Static RAM or for a flip flop.

Dependencies are inferred from the claim text.