Fabrication of interpoly dielctric for EPROM-related technologies

In a semiconductor process for fabricating an electrically programmable memory device which includes the steps of:

• providing a substrate;
• forming a thin gate oxide over a portion of said substrate;
• depositing a first polysilicon layer over said thin gate oxide;
• forming a composite dielectric over said first polysilicon layer;
• and
• forming a control electrode over said dielectric;
• an improved method for forming said dielectric which reduces long-term charge loss in said device, said improved method comprising the steps of:
• (a) optionally forming a silicon dioxide layer over said first polysilicon electrode, said silicon dioxide layer being formed by oxidizing said first polysilicon layer;
• (b) depositing a silicon nitride layer over said silicon dioxide layer or said first polysilicon layer if no silicon dioxide is formed, said silicon nitride layer having a thickness of 150 .ANG. or less;
• and
• (c) chemically depositing an oxide film over said nitride layer, said oxide film being substantially as thick as, or thicker than, said silicon nitride layer.

In a semiconductor process for fabricating an electrically programmable memory device which includes the steps of:

• providing a substrate;
• forming a thin gate oxide over a portion of said substrate;
• depositing a first polysilicon layer over said thin gate oxide;
• forming a composite dielectric over said first polysilicon layer;
• and
• forming a control electrode over said composite dielectric;
• an improved method for forming said composite dielectric reduces long-term charge loss in said device, said improved method comprising the steps of:
• (a) optionally forming a silicon dioxide layer over said first polysilicon electrode;
• (b) depositing a silicon nitride layer over said silicon dioxide layer, said silicon nitride layer having a thickness of 150 .ANG. or less;
• and
• (c) chemically depositing an oxide film over said nitride layer, said oxide film being substantially as thick as, or thicker than, said silicon nitride layer, wherein said oxide film also forms at least a portion of the gate dielectric of peripheral transistors, said gate dielectric comprises approximately 50-100 .ANG. of said oxide deposited over approximately 10-100 .ANG. of thermal oxide.

In a semiconductor process for making an electrical programmable memory device, a method for fabricating a composite dielectric layer over a first polysilicon electrode to inhibit long-term charge loss in said device comprising the steps of:

• (a) forming a first silicon oxide layer over said first polysilicon electrode;
• (b) depositing a silicon nitride layer over said first silicon oxide layer, said silicon nitride layer being thicker than said first silicon dioxide layer;
• (c) depositing a second silicon dioxide layer over said nitride layer, said second oxide layer having a thickness which is greater than that of said first oxide layer and greater than or equal to that of said silicon nitride layer, said second oxide layer being at least 50 .ANG. thick;
• and
• (d) forming a polysilicon control gate over said second silicon dioxide layer;
• said second silicon dioxide layer reducing charge loss from either said first polysilicon electrode or said silicon nitride layer when said control electrode is at a sufficiently high positive potential to program said device, and
• wherein said composite dielectric has a capacitively measured effective thickness of 200 .ANG. or less.

In a semiconductor process for fabricating an electrically programmable memory device which includes the steps of:

• providing a substrate;
• forming a thin gate oxide over a portion of said substrate;
• depositing a first polysilicon layer over said thin gate oxide;
• forming a composite dielectrical over said silicon layer;
• and forming a polysilicon control electrode over said composite dielectric;
• an improved method method for forming said composite dielectric which reduces long-term charge loss in said device, said improved method comprising the steps of:
• (a) optionally forming a silicon dioxide layer over said first polysilicon electrode by oxidizing said first polysilicon layer;
• (b) depositing a silicon nitride layer over said silicon dioxide layer, said silicon nitride layer having a thickness of 150 .ANG. or less;
• (c) chemically depositing an oxide film over said nitride layer, said oxide film being at least as thick as said silicon nitride layer to reduce electron flow to said control electrode;
• (d) wherein said composite dielectric has a capacitively measured effect oxide thickness of 250 .ANG. or less.