Internally decoupled integrated circuit package
AssigneeRogers Corporation
InventorsJorge M. Hernandez, Michael S. Hyslop
Life of this patent
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Abstract
A decoupling scheme is presented which is well suited for use with any type of integrated circuit package. In accordance with the present invention, a flat decoupling capacitor is attached directly to the top of an IC die and is electrically connected to the IC by means of raised conductive bumps provided either on the surface of the decoupling capacitor or on the IC die surface. These conductive bumps interconnect the internal electrodes of the capacitor to the power and ground circuits of the IC. The resulting decoupling scheme provides a decoupling loop with an inductance which is significantly lower than previously disclosed decoupling loops.
Claims28
An integrated circuit package comprising:
- a housing;
- an integrated circuit (IC) chip in said housing, said IC chip including a planar surface having a first plurality of contact pads peripherally arranged therealong and a second plurality of contact pads spaced inwardly from said first pads, said second pads corresponding to voltage and/or ground connections of said IC chip;
- a decoupling capacitor on said planar surface of said IC chip, said decoupling capacitor including a planar surface having a third plurality of contact pads arranged in a pattern corresponding to said second pads on said IC chip;
- and
- connecting means for electrically interconnecting said second and third pads wherein said decoupling capacitor is electrically connected to said voltage and/or ground connections of said IC chip.
An integrated circuit chip comprising:
- a block of semi-conductive material including a planar surface having a first plurality of contact pads peripherally arranged therealong and a second plurality of contact pads spaced inwardly from said first pads, said second pads corresponding to voltage and/or ground connections of said IC chip.
A decoupling capacitor comprising:
- a non-conductive support substrate;
- a first electrode on said support substrate;
- at least one layer of dielectric material on said first electrode;
- a second electrode on said layer of dielectric material with said dielectric material being sandwiched between said first and second electrodes;
- a non-conductive layer on said second electrode;
- a plurality of spaced first conductive vias extending from said first electrode through said dielectric material, said second electrode and said non-conductive layer;
- a plurality of spaced second conductive vias extending from said second electrode and through said non-conductive layer;
- and
- a plurality of contact pads on said non-conductive layer, said first and second vias terminating at said contact pads.
Dependencies are inferred from the claim text.