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US 5,091,328 AGranted
Method of late programming MOS devices
AssigneeNational Semiconductor Corporation
InventorWilliam E. Miller
Life of this patent
Estimating the term…
Abstract
Method for late programming of MOS integrated circuit devices. A second or third level conductive layer is used as a device selection mask for transporting dopant from a doped gate (formed from a first level conductive layer) into the channel region of selected field effect transistors.
Claims30
A method for late programming integrated circuits, comprising the steps:
- a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with dopant;
- b) depositing a first insulating layer, having an upper surface, over said field effect transistor;
- c) opening contact windows in said first insulating layer over said source and said drain;
- d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain;
- e) opening a late programming window in said second level conductive layer over said doped gate;
- and
- f) transporting said dopant from said doped gate into said channel region of said field effect transistor.
4 more elements
A method for late programming integrated circuits, comprising the steps:
- a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with dopant;
- b) depositing a first insulating layer, having an upper surface, over said field effect transistor;
- c) opening contact windows in said first insulating layer over said source and said drain;
- d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain;
- e) said second level conductive layer is etched to define source and drain electrodes;
- f) depositing a second insulating layer, having an upper surface;
- g) depositing an initial third level conductive layer on said upper surface of said second insulating layer;
- h) opening a late programming window in said initial third level conductive layer over said doped gate;
- and
- i) transporting said dopant from said doped gate into said channel region of said field effect transistor.
7 more elements
A method for late programming integrated circuits, comprising the steps:
- a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer;
- b) doping said gate with dopant;
- c) depositing a first insulating layer, having an upper surface, over said field effect transistor;
- d) opening contact windows in said first insulating layer over said source and said drain;
- e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain;
- f) opening a late programming window in said second level conductive layer over said doped gate;
- and
- g) transporting said dopant from said doped gate into said channel region of said field effect transistor.
5 more elements
A method for late programming integrated circuits, comprising the steps:
- a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer;
- b) doping said gate with dopant;
- c) depositing a first insulating layer, having an upper surface, over said field effect transistor;
- d) opening contact windows in said first insulating layer over said source and said drain;
- e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain;
- f) said second level conductive layer is etched to define source and drain electrodes;
- g) depositing a second insulating layer, having an upper surface;
- h) depositing an initial third level conductive layer on said upper surface of said second insulating layer;
- i) opening a late programming window in said initial third layer conductive layer over said doped gate;
- and
- j) transporting said dopant from said doped, gate into said channel region of said field effect transistor.
8 more elements
A method for late programming integrated circuits, comprising the steps:
- a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with one or more dopants, including a selected dopant;
- b) depositing a first insulating layer, having an upper surface, over said field effect transistor;
- c) opening contact windows in said first insulating layer over said source and said drain;
- d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said t windows to make a low resistance electrical on with said source and said drain;
- e) opening a late programming window in said second level conductive layer over said doped gate;
- and
- f) transporting said selected dopant from said doped gate into said channel region of said field effect transistor.
4 more elements
A method for late programming integrated circuits, comprising the steps:
- a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with one or more dopants, including a selected dopant;
- b) depositing a first insulating layer, having an upper surface, over said field effect transistor;
- c) opening contact windows in said first insulating layer over said source and said drain;
- d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain;
- e) said second level conductive layer is etched to define source and drain electrodes;
- f) depositing a second insulating layer, having an upper surface;
- g) depositing an initial third level conductive layer on said upper surface of said second insulating layer;
- h) opening a late programming window in said initial third level conductive layer over said doped gate;
- and
- i) transporting said selected dopant from said doped gate into said channel region of said field effect transistor.
7 more elements
A method for late programming integrated circuits, comprising the steps:
- a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer;
- b) doping said gate with one or more dopants, including a selected dopant;
- c) depositing a first insulating layer, having an upper surface, over said field effect transistor;
- d) opening contact windows in said first insulating layer over said source and said drain;
- e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain;
- f) opening a late programming window in said second level conductive layer over said doped gate;
- and
- g) transporting said selected dopant from said doped gate into said channel region of said field effect transistor.
5 more elements
A method for late programming integrated circuits, comprising the steps:
- a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer;
- b) doping said gate with one or more dopants, including a selected dopant;
- c) depositing a first insulating layer, having an upper surface, over said field effect transistor;
- d) opening contact windows in said first insulating layer over said source and said drain;
- e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain;
- f) said second level conductive layer is etched to define source and drain electrodes;
- g) depositing a second insulating layer, having an upper surface;
- h) depositing an initial third level conductive layer on said upper surface of said second insulating layer;
- i) opening a late programming window in said initial third layer conductive layer over said doped gate;, and
- j) transporting said selected dopant from said doped gate into said channel region of said field effect transistor.
7 more elements
Dependencies are inferred from the claim text.