US 5,087,829 A · High speed clock distribution system

Abstract

This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.

Claims21

Dependent claims

A clock distribution system comprising:

a clock signal generation block for generating a one-phase reference clock;
a first control means for comparing a phase of said reference clock with a phase of a feedback signal and controlling the phase of said reference clock so that the phases are coincident with each other and providing a phase adjusted reference clock;
a delay circuit having a plurality of variable delay circuits which are connected in series and to which said phase adjusted reference clock is inputted;
means for generating multi-phase clock signals in response to output signals of said plurality of variable delay circuits and said phase-adjusted reference clock;
and
a second control means for comparing a delay time of said plurality of variable delay circuits with a period of said phase-adjusted reference clock and controlling the delay time of said plurality of variable delay circuits so as to establish a predetermined relation with the period of said phase-adjusted reference clock, wherein one of said multi-phase clock signals is applied as said feedback signal to said first control means.

3 more elements

In a clock distribution system for a computer which includes a clock signal generation block, signal paths and a plurality of processing units and wherein a predetermined first clock signal is distributed to said plurality of processing units from the output of said clock generation block through said signal paths with each processing unit including:

means for aligning a phase of said first clock signal with a phase of a second clock signal and providing a phase-adjusted first clock signal;
a delay circuit group of a plurality of variable delay circuits which each have an equal delay time, are connected in series and receive said phase-adjusted first clock signal;
means for generating multi-phase second clock signals in response to output signals from said plurality of variable delay circuits and said phase-adjusted first clock signal;
and
means for controlling the delay time of said plurality of said variable delay circuits to be less than the period of said first clock signal.

2 more elements

In a clock distribution system for a computer which includes a clock signal generation block, signal paths and a processing unit and in which a phase-adjusted clock signal is supplied to said processing unit from an output of said clock signal generation block through said signal paths, a clock distribution system comprising:

means for aligning a phase of a one-phase first clock signal with a phase of a second clock signal, disposed in said clock signal generation block, so that a phase aligned one-phase first clock signal is supplied as said phase-adjusted first clock signal to said first processing unit as a destination;
a delay circuit group of a plurality of series connected variable delay circuits receiving said first clock signal, said delay circuit group being disposed in said processing unit;
means for generating multi-phase second clock signals in response to output signals of each of said plurality of variable delay circuits and said phase-adjusted first clock signal, said means for generating being disposed in said processing unit and one of said multi-phase second clock signals being provided to said means for aligning;
and
means for controlling a delay time of said plurality of delay circuits so that the delay time is less than a period of said first clock signal, said means for controlling being disposed in said processing unit.

2 more elements

Dependencies are inferred from the claim text.

High speed clock distribution system

Life of this patent

High speed clock distribution system

Life of this patent

Abstract

Claims21