US 5,086,477 A · Automated system for extracting design and layout information from an integrated circuit

Abstract

A system for extracting design information from a semiconductor integrated circuit (IC) is disclosed. The system includes a microscope and camera for capturing a composite image of the IC in the form of a video signal. Image capture occurs on a section-by-section basis in which a "snapshot" of each section is taken, the die-holding table stepped to a new section, and a snapshot of the new section obtained. This image capture operation continues until a composite image of the IC is obtained by successive capture of contiguous or partially overlapping images covering all of the different sections of the die. An image processor receives the video signal from the optical means and generates an abstract representation of the die in the form of lists of identifying features such as the size, type and relative location of all transistors, and the width, length and relative location of all of the metal interconnects to the IC. These lists are subsequently compared with reference library circuits by a computer to recognize individual circuit cells. Once all of the ciruit cells on the die have been recognized, the computer then generates a schematic netlist of the IC.

Claims35

Dependent claims

A system for extracting design information from a semiconductor integrated circuit (IC) comprising:

means for capturing the image of a section of said IC in the form of a video signal;
table means for placing said IC in position for image capture of said section by said capture means, said table means being responsive to a control signal to enable said IC to be repositioned relative to said capture means such that a composite image of said IC can be obtained by successive capture of partially contiguous or overlapping images covering all of the different sections of said IC;
image processing means for receiving said video signal and for generating an abstract representation of said images, said abstract representation including lists of identifying features of each of said sections and the relative locations of said identifying features;
memory means for storing said images, said abstract representations and a reference library of circuit elements;
computer means coupled to said image processing and memory means for combining said abstract representations of said images to obtain said composite image, and for recognizing individual circuit cells by matching the abstract representation of a portion of said composite image with a corresponding entry in said reference library;
once all of said circuit cells on said IC have been recognized, said computer means generating a schematic representation of said IC in the form of a netlist.

3 more elements

A system for extracting design information from a semiconductor integrated circuit (IC) comprising:

optical means for capturing the image of a section of said IC in the form of a video signal;
table means for placing said IC in position for image capture of said section by said optical means, said table means being responsive to a control signal to enable said IC to be positioned relative to said optical means such that a composite image of said IC can be obtained by successive capture of contiguous or partially overlapping images covering all of the different sections of said IC;
image processing means for receiving said video signal and for generating an abstract representation of said images, said abstract representation including lists of identifying features of each of said sections and the relative locations of said identifying features;
memory means for storing said images, said abstract representations and a reference library of circuit elements;
computer means coupled to said image processing and memory means for combining said abstract representations of said images to obtain said composite image, and for recognizing individual circuit cells by using their abstract representations to identify circuit components within said cells and to decipher their interconnections therefrom, each of said recognized cells being input into said reference library for subsequent recognition of other instances of said cells;
once all of said circuit cells on said IC have been recognized, said computer means generating a schematic representation of said IC in the form of a netlist.

3 more elements

In a computer system capable of receiving and processing video signals, a process for extracting design information from an integrated circuit (IC) comprising the steps of:

(a) inputting a magnified image of one layer of said IC into said computer system by successively capturing tiled images of all of the various sections of said IC;
(b) processing said magnified image of said one layer to generate an abstract representation of said IC, said abstract representation including lists of features detected in said image and their relative positions, said lists providing a means by which individual circuit cells can be identified;
(c) repeating steps (a) and (b) until all layers necessary for circuit recognition have been captured;
(d) combining the abstract representations associated with each of said layers to form a single intermediate representation of said IC;
(e) utilizing a reference library of circuits stored in an intermediate representation within said computer system to recognize instances of said circuits on said IC;
(f) overlaying said recognized instances with schematic representations of said circuits;
(g) repeating steps (e) and (f) until all circuit elements on said IC and their associated connections have been processed;
(h) optionally overlaying the schematics of groups of connected circuit elements with a high level circuit representation indicative of the functionality of said connected elements;
and
(i) outputting a schematic netlist of said IC.

7 more elements

Dependencies are inferred from the claim text.

Automated system for extracting design and layout information from an integrated circuit

Life of this patent

Automated system for extracting design and layout information from an integrated circuit

Life of this patent

Abstract

Claims35