Ferroelectric capacitor and memory cell including barrier and isolation layers

A ferroelectric capacitor structure for fabrication on a semiconductor substrate, comprising:

• a dielectric layer formed on a surface of said substrate;
• a diffusion barrier layer formed on a surface of said dielectric layer;
• an isolation layer formed on a surface of said diffusion barrier layer;
• a bottom electrode formed on a portion of a surface of said isolation layer;
• a ferroelectric layer formed partially on the surface of said isolation layer and partially on the surface of said bottom electrode, wherein said isolation layer prevents contact between said diffusion barrier layer and said ferroelectric layer, said diffusion barrier layer prevents diffusion of material of said ferroelectric layer into said dielectric layer or said substrate;
• and
• a top electrode formed on a surface of said ferroelectric layer.

A ferroelectric capacitor structure for integrated fabrication with MOS devices on a semiconductor substrate, comprising:

• a dielectric layer formed on said semiconductor substrate;
• a barrier layer formed on said dielectric layer for preventing diffusion of ferroelectric material therethrough;
• an isolation layer formed on said barrier layer for providing electrical isolation with respect to said barrier layer;
• a bottom conductive electrode formed on said isolation layer, said bottom electrode defining a bottom plate of said ferroelectric capacitor structure;
• a layer of ferroelectric material formed on said bottom electrode, said ferroelectric material defining a polarizable dielectric of said ferroelectric capacitor structure;
• a top conductive electrode formed on said ferroelectric material layer, said top electrode defining a top plate of said ferroelectric capacitor structure;
• and
• conductive interconnect paths for interconnecting the top and bottom electrodes to a respective MOS device.