US 5,003,062 A · Semiconductor planarization process for submicron devices

Abstract

A method is described for planarization of dielectric layers between conductor layers in multilayer metallurgy of submicron integrated circuit devices. The method begins with the integrated circuit intermediate product having devices, such as FETs or bipolar formed therein, but before interconnection metallurgy has been formed on the principal surface of the product. The principal surface has a patterned conductive layer at its surface. The spin-on-glass sandwich now is begun to be formed by depositing a silicon dioxide coating over the patterned conductor layer. A first layer of spin-on-glass is deposited upon the silicon dioxide coating. The layer is baked at a temperature of less than about 350 degrees C. Vacuum degassing of the coating at less than about 100 mtorr and 350 degrees C. effectively overcomes the outgassing problem by removing unwanted gases in the glass layer at this point in the process. The spin-on-glass layer process just given is repeated for subsequent layers of spin-on-glass until the desired thickness of planarized spin-on-glass dielectric layer has been formed. The layers are then cured at a temperature of less than about 500 degrees C. The second layer of silicon dioxide coating over the spin-on-glass dielectric layer completes the planarization. A vacuum degassing step is performed just before the deposition of the next conductor layer.

Claims19

Dependent claims

Method for planarization of dielectric layers between conductor layers in multilayer metallurgy of submicron IC devices comprising:

providing a semiconductor substrate having FET devices formed within and on its surface and with at least one patterned conductive layer thereover;
depositing a silicon dioxide coating over said patterned conductor layer;
covering the said silicon dioxide coating with a spin-on-glass layer having a thickness of less than about 1.0 micrometers, baking the said coating at a temperature less than about 350 degree C., vacuum degassing the said coating at less than about 100 mtorr and 350 degrees C.;
repeating said covering with spin-on-glass, baking and vacuum degassing processes at least one more time until the desired thickness of planarized spin-on-glass dielectric layer is formed;
curing the said spin-on-glass dielectric layer;
and depositing a silicon dioxide coating over said spin-on-glass dielectric layer to complete said planarization.

3 more elements

Method for fabricating a submicrom IC semiconductor device comprising:

forming individual semiconductor devices within and on a semiconductor substrate;
and forming a multilayer metallurgy structure over and connected to said devices to produce said IC semiconductor device;
the planarization of the dielectric layers between conductive layers in said multilayer metallurgy structure is made by depositing a silicon dioxide coating over an already patterned conductor layer;
covering the said silicon dioxide coating with a spin-on-glass layer having a thickness of less than about 1.0 micrometers, baking the said coating at a temperature less than about 350 degrees C., vacuum degassing the said coating at less than about 100 mtorr and 350 degrees C.;
repeating said covering with spin-on-glass, baking and vacuum degassing processes at least one more time until the desired thickness of planarized spin-on-glass dielectric layer is formed;
curing the said spin-on-glass dielectric layer;
and depositing a silicon dioxide coating over said spin-on-glass dielectric layer to complete said planarization.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor planarization process for submicron devices

Life of this patent

Semiconductor planarization process for submicron devices

Life of this patent

Abstract

Claims19