Sense amplifier and method for sensing the outputs of static random access memory cells
AssigneeTexas Instruments Incorporated
InventorHiep V. Tran
Life of this patent
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Abstract
A sense amplifier (10) is provided for with use with a static random access memory. Cascode preamplifier transistors (20a, 20b) convert the complementary currents appearing on bitlines (14a, 14b) coupled to the complementary outputs BIT and BIT of a memory cell (12). The currents are converted into differential voltages and amplified into emitter coupled logic compatible voltages which are output from sense amplifier (10) on DATA line (30a) and DATA line (30b). In a preferred embodiment, a first feedback loop is provided from DATA line (30b) to preamplifying transistor (20a) and a second feedback loop is provided from DATA line (30a) to preamplifier transistor (20b).
Claims21
A sense amplifier for use with a random access memory cell having complementary outputs, comprising:
- a first preamplifier for converting a first current from a first complementary output of said memory cell into a first differential voltage signal;
- a second preamplifier for converting a second current from a second complementary output of said memory cell into a second differential voltage signal;
- a differential amplifier for amplifying said first and second differential voltage signals;
- and
- first and second sense amplifier complementary outputs for outputting first and second amplified differential voltage signals.
A sense amplifier for use with a column of memory cells, each cell in the column having a pair of complementary outputs connected to respective bit lines of a pair of bitlines forming each column, comprising:
- a first preamplifier transistor coupled to a first bitline of a column of memory cells;
- a second preamplifier transistor coupled to a second bitline of a column of memory cells;
- first and second emitter coupled amplifier transistors forming a differential amplifier, said first amplifier transistor coupled to said first preamplifier transistor, and said second amplifier transistor coupled to said second preamplifier transistor;
- said amplifier transistors including first and second sense amplifier outputs;
- a first feedback circuit providing a first feedback path from a said sense amplifier output to said first preamplifier transistor;
- and
- a second feedback circuit providing a second feedback path from another said sense amplifier output to said second preamplifier transistor.
A sense amplifier for use with a memory cell having first and second complementary outputs, comprising;
- a first cascode preamplifying transistor, the emitter of said first preamplifying transistor connected to a first memory cell complementary output;
- a second cascode preamplifying transistor, the emitter of said second preamplifying transistor connected to a second memory cell complementary output;
- a differential amplifier comprising first and second emitter coupled amplifying transistors, said first amplifying transistor coupled to said first preamplifying transistor, said second amplifying transistor coupled to said second preamplifying transistor;
- first and second sense amplifier complementary outputs;
- a first feedback circuit providing a feedback path between said first sense amplifier complementary output and the emitter of said first preamplifying transistor;
- and
- a second feedback circuit providing a feedback path between said second sense amplifier complementary output and the emitter of said second preamplifying transistor.
A method for sensing the complementary output of a random access memory cell, comprising the steps of:
- converting a first complementary output current of the memory cell into a first voltage signal;
- converting a second complementary output current of the memory cell into a second voltage signal;
- and
- differentially amplifying said first and second voltage signals to provide first and second output signals.
A method for sensing the complementary output of a selected memory cell in an array of memory cells formed in columns and in rows, each column having a first and second bitlines and each row having a wordline, comprising the steps of:
- selecting the row containing the selected cell by applying a voltage to the wordline forming the row;
- selecting the column containing the selected memory cell by gating the first and second bitlines to a sense amplifier;
- converting the current on the first bitline into a first voltage signal;
- converting the current on the second bitline into a second voltage signal;
- and
- differentially amplifying the first and second voltage signals.
Dependencies are inferred from the claim text.