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US 4,990,796 AGranted
Tristable multivibrator
OwnerEdgar D. Olsoninventor
Life of this patent
Estimating the term…
Abstract
Disclosed is a circuit which provides the controlled generation of tri-level digital signals utilizing Field Effect Transistors (FETs), as active elements. The stability of all three states is due to a unique feed-back technique, and utilization of the gate threshold characteristics of FETs. This circuit is controllable with either bi-level or tri-level digital signals, and is externally configurable as: a ternary up counter, providing the count sequence of 0,1,2,0 . . . ; a ternary down counter, providing the count sequence of 2,1,0,2 . . . ; a ternary shift left/right register; or as a ternary memory.
Claims19
The tristable multivibrator as set forth in claim 4, wherein the switching circuitry means connected to the lines comprises:
- A tristable multivibrator comprising:
- a first input line connected to a first output line;
- a second input line connected to a second output line;
- a third input line connected to a third output line;
- a first switch connected to the first input and output lines on one side, connected to a first resistor in series with and between the first switch and a first source of electric potential on another side, and connected to the third input and output lines such that when the third input line is at an electric potential sufficiently different than that of the first source of electric potential, the first switch turns on and allows transmission of electric potential from the first source of electric potential to the first input and output lines, and vice-versa such that when the third input line is not at an electric potential sufficiently different than that of the first source of electric potential, the first switch turns off and prevents transmission of electric potential from the first source of electric potential to the first input and output lines, thereby controlling transmission of electric potential from the first source of electric potential to the first input and output lines;
- a second switch connected to the first input and output lines on one side, connected to a second resistor in series with and between the second switch and a second source of electric potential on another side, and connected to the second input and output lines such that when the second input line is at an electric potential sufficiently different than that of the second source of electric potential, the second switch turns on and allows transmission of electric potential from the second source of electric potential to the first input and output lines, and vice-versa, thereby controlling transmission of electric potential from the second source of electric potential to the first input and output lines;
- a third switch connected to the second input and output lines on one side, connected to a third resistor in series with and between the third switch and the first source of electric potential on another side, and connected to the first input and output lines such that when the first input line is at an electric potential sufficiently different than that of the first source of electric potential, the third switch turns on, and vice-versa, thereby controlling transmission of electric potential from the first source of electric potential to the second input and output lines;
- a fourth switch connected to the second input and output lines on one side, connected to a fourth resistor in series with and between the fourth switch and the second source of electric potential on another side, and connected to the third input and output lines such that when the third input line is at an electric potential sufficiently different than that of the second source of electric potential, the fourth switch turns on, and vice-versa, thereby controlling transmission of electric potential from the second source of electric potential to the second input and output lines;
- a fifth switch connected to the third input and output lines on one side, connected to a fifth resistor in series with and between the fifth switch and the first source of electric potential on another side, and connected to the second input and output lines such that when the second input line is at an electric potential sufficiently different than that of the first source of electric potential, the fifth switch turns on, and vice-versa, thereby controlling transmission of electric potential from the first source of electric potential to the third input and output lines;
- and
- a sixth switch connected to the third input and output lines on one side, connected to a sixth resistor in series with and between the sixth switch and the second source of electric potential on another side, and connected to the first input and output lines such that when the first input line is at an electric potential sufficiently different than that of the second source of electric potential, the sixth switch turns on, and vice-versa, thereby controlling transmission of electric potential from the second source of electric potential to the third input and output lines.
8 more elements
A three-state data register comprising:
- clock circuitry means for controlling loading of data into the data register;
- reset circuitry means for placing the data register in a known state of output, said reset circuitry means connected to the clock circuitry means;
- and
- data circuitry means for the reception and transmission of data, such that when a data signal is presented to and loaded into the data register, said data signal is maintained and passed on to a primary output and two separate distinct signals are generated as supplementary outputs, said data circuitry means connected to the reset circuitry means and the clock circuitry means.
1 more element
A ternary counter comprising:
- at least one ternary data register having clock, reset, and data inputs and also having X, Y, and Z outputs, the X output transmitting a signal present at the data input when the ternary data register received that signal, the Y output transmitting a signal corresponding to the signal at the X output increased by a digital value, and the Z output transmitting a signal corresponding to the signal at the X output decreased by a digital value;
- a count input line connected to the clock input of a first ternary data register for transmission thereto of counting signals;
- a clear input line connected to reset inputs of ternary data registers comprising the ternary counter so that the ternary counter can be placed in a known output state;
- and
- an output connection connecting a ternary data register output to the data input of that same ternary data register.
2 more elements
Dependencies are inferred from the claim text.