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US 4,975,595 AGranted
Scannable register/latch circuit
AssigneeNational Semiconductor Corporation
InventorsScott Roberts, Daniel Chang
Life of this patent
Estimating the term…
Abstract
A circuit is described for functioning as a transparent latch, a latch where the data is determined by the state of a data signal at the time a signal changes state, a D-type flip-flop, and a scan path element. The mode of operation of the circuit is determined by the condition of respective ones of a set of control signals.
Claims25
A multifunctional circuit, controlled by a set of control signals, for supplying an output data signal to a circuit output terminal
- a master latch circuit, having a data input terminal to receive a first data input signal, for providing a master output data signal at a master output terminal;
- a salve latch circuit connected to the circuit output terminal, having a slave data input terminal to receive the first data input signal and having a master data input terminal connected to the master output terminal;
- and
- first and second slave switches, included in said slave circuit and with the first slave switch responsive to a latch clock signal and the second slave switch responsive to a master clock signal, with said first and second switches for causing the slave circuit to provide the first data input signal received at the slave input terminal directly to the circuit output terminal when the latch clock signal is asserted and the master clock signal is not asserted, for causing the slave circuit to latch a signal currently on the circuit output terminal when the latch clock signal is not asserted and the master clock signal is not asserted and for causing the slave circuit to receive data from the master circuit output terminal and supply that received data directly to the circuit output terminal when the master clock signal is asserted and the latch clock signal is not asserted;
- a first master switch, included in said master latch and responsive to said master clock signal, for causing said master latch to latch data onto said master latch terminal when said master clock signal is asserted so that said multifunctional circuit may function either as a transparent latch, a latch, or a D type flip-flip under control of said latch clock and master clock signals.
2 more elements
A bipolar circuit comprising:
- a first pair of transistors having emitters connected together and through a first transistor to a first node;
- a base of a first one of the first pair being coupled through a first terminal to a collector of the second one of the first pair and a base of the second one of the first pair being coupled through a second terminal to a collector of the first one of the first pair;
- a second pair of transistors having emitters connected together and through a second transistor to a second node, a first one of the second pair having a collector connected to the second terminal and a base connected to a reference potential, a second one of the first pair having a collector connected to the first terminal and a base connected to receive an input signal;
- and
- a third pair of transistors having emitters connected together and through a third transistor to the second node, a first one of the third pair having a collector connected to the second terminal and a base connected to receive scan data, a second one of the third pair having a collector connected to the first terminal and a base connected to receive scan data.
2 more elements
An emitter coupled logic (ECL) circuit structure for receiving register input data and register scan input data, that selectively functions as a register to transfer the received register input data to a set of output terminals (register mode), as a scan register to transfer the received scan register data to the output terminals (scan mode), or as a latch element for the received register data (latch mode), with the circuit structure including coupled master and slave latches, said structure comprising:
- a register mode (RM) pair of emitter coupled transistors, included in said master latch, with a right hand side transistor (RHS) in said RM pair having its collector coupled to a master RHS terminal and with a left hand side (LHS) transistor in said RM pair having its collector coupled to a master LHS terminal, and with the bases of the transistors in said RM pair coupled to receive the register input data;
- an RM select transistor having its collector coupled to the coupled emitters of said RM transistor pair, its emitter coupled to a master constant current source, and its base coupled to receive an RM select signal;
- a scan mode (SM) pair of emitter coupled transistors, included in said master latch, with an RHS transistor in said SM pair having its collector coupled to said master RHS terminal and with an LHS transistor in said RM pair having its collector coupled to said master LHS terminal, with the bases of the transistors in said SM pair coupled to receive the scan register input data;
- an SM select transistor having its collector coupled to the coupled emitters of said SM transistor pair, its emitter coupled to said master constant current source, and its base coupled to receive an SCLK select signal;
- a master latch mode (MLM) pair of emitter coupled transistors, included in said master latch, with an RHS transistor in said MLM pair having its collector coupled to said master RHS terminal and with an LHS transistor in said MLM pair having its collector coupled to said master LHS terminal, with the base of RHS transistor in said MLM pair coupled to said master LHS terminal and with the base of the LHS transistor in said MLM pair coupled to said master RHS terminal;
- an MLM select transistor having its collector coupled to the coupled emitters of said MLM transistor pair, its emitter coupled to said master constant current source, and its base coupled to receive a MCLK select signal;
- means for generating a set of voltage levels V.sub.CL, V.sub.C, V.sub.CH, and V.sub.SCLKH with the magnitudes of said voltage levels selected so that V.sub.CL <V.sub.C <V.sub.CH <V.sub.SCLKH ;
- and
- means for controllably setting the magnitudes of said RM, SCLK, and MCLK select signals to selected ones of said voltage levels to couple either the emitters of said RM pair to said master current source to establish voltage levels at said master RHS and LHS terminals corresponding to the register input data, to couple the emitters of said SM pair to said master current source to establish voltage levels at said master RHS and LHS terminals corresponding to the scan register input data, or to couple the emitters of said LM pair to said master current source to latch the previously established RM or SM voltage levels on said master RHS and LHS terminals wherein MCLK swings around V.sub.C and SCLK swings around MCLK so that SCLK runs on an expanded swing and overrides MCLK.
6 more elements
An emitter coupled logic (ECL) circuit structure for receiving register input data and register scan input data, that selectively functions as a register to transfer the received register input data to a set of output terminals (register mode), as a scan register to transfer the received scan register data to the output terminals (scan mode), or as a latch element for the received register data (latch mode), with the circuit structure including coupled master and slave latches, said structure comprising:
- a register mode (RM) pair of emitter coupled transistors, included in said master latch, with a right hand side transistor (RHS) in said RM pair having its collector coupled to a master RHS terminal and with a left hand side (LHS) transistor in said RM pair having its collector coupled to a master LHS terminal, and with the bases of the transistors in said RM pair coupled to receive the register input data;
- an RM select transistor having its collector coupled to the coupled emitters of said RM transistor pair, its emitter coupled to a master constant current source, and its base coupled to receive an RM select signal;
- a scan mode (SM) pair of emitter coupled transistors, included in said master latch, with an RHS transistor in said SM pair having its collector coupled to said master RHS terminal and with an LHS transistor in said RM pair having its collector coupled to said master LHS terminal, with the bases of the transistors in said SM pair coupled to receive the scan register input data;
- an SM select transistor having its collector coupled to the coupled emitters of said SM transistor pair, its emitter coupled to said master constant current source, and its base coupled to receive an SM select signal being the inverted RM select signal;
- a master latch mode (MLM) pair of emitter coupled transistors, included in said master latch, with an RHS transistor in said MLM pair having its collector coupled to said master RHS terminal and with an LHS transistor in said MLM pair having its collector coupled to said master LHS terminal, with the base of RHS transistor in said MLM pair coupled to said master LHS terminal and with the base of the LHS transistor in said MLM pair coupled to said master RHS terminal;
- an MLM select transistor having its collector coupled to the coupled emitters of said MLM transistor pair, its emitter coupled to said master constant current source, and its base coupled to receive a MCLK select signal;
- means for generating a set of voltage levels V.sub.CL, V.sub.C, and V.sub.CH with the magnitudes of said voltage levels selected so that V.sub.CL <V.sub.C <V.sub.CH ;
- and
- means for controllably setting the magnitudes of said RM and MCLK select signals to selected ones of said voltage levels to couple either the emitters of said RM pair to said master current source to establish voltage levels at said master RHS and LHS terminals corresponding to the register input data, to couple the emitters of said SM pair to said master current source to establish voltage levels at said master RHS and LHS terminals corresponding to the scan register input data, or to couple the emitters of said LM pair to said master current source to latch the previously established RM or SM voltage levels on said master RHS and LHS terminals.
6 more elements
Dependencies are inferred from the claim text.