Method for forming a transistor base region under thick oxide

An integrated circuit structure formed in a semiconductor body, comprising:

• an MOS transistor, comprising:
• a source region diffused into said semiconductor body;
• a drain region diffused into said semiconductor body;
• a gate dielectric overlying a channel region disposed between said source and drain regions;
• and
• a gate electrode, comprising polysilicon and overlying said gate dielectric;
• and
• a diffused resistor, comprising:
• a diffused region formed into said semiconductor body at a distance away from said MOS transistor;
• a resistor dielectric overlying said diffused region, said resistor dielectric of a thickness greater than the thickness of said gate dielectric;
• a polysilicon layer, having substantially the same thickness and conductivity as said gate electrode and overlying said resistor dielectric;
• and
• contact diffusions, formed at opposing ends of said diffused region and self-aligned with said polysilicon layer.

An integrated circuit structure formed into a semiconductor body, comprising:

• an MOS transistor, comprising:
• a source region of a first conductivity type diffused into said semiconductor body;
• a drain region of said first conductivity type diffused into said semiconductor body;
• a gate dielectric overlying a channel region disposed between said source and drain regions;
• and
• a gate electrode, comprising doped polycrystalline silicon and overlying said gate dielectric;
• and
• a bipolar transistor, comprising:
• a collector region of a second conductivity type disposed within said semiconductor body at a distance away from said MOS transistor;
• a base region of said first conductivity type disposed within said collector region;
• an emitter region of said second conductivity type disposed within said base region;
• a base dielectric overlying said base and emitter regions, the thickness of said base dielectric being greater than the thickness of said gate dielectric of said MOS transistor;
• an emitter electrode comprising doped polycrystalline silicon and overlying said base dielectric, and making contact to said emitter region through a contact via formed through said base dielectric, the portion of said emitter electrode overlying said base dielectric having substantially the same thickness and conductivity as said gate electrode;
• a base contact region of said first conductivity type disposed within said base region, said base contact region having substantially the same depth as said source and drain regions of said MOS transistor and being self-aligned to said emitter electrode;
• an isolation dielectric disposed adjacent said base contact region;
• and
• an interconnect disposed upon the surface of said base contact region and extending onto said isolation dielectric, said interconnect comprising titanium nitride.