US 4,951,175 A · Semiconductor memory device with stacked capacitor structure and the manufacturing method thereof

Abstract

A dynamic random access memory with a stacked capacitor cell structure is disclosed which has a memory cell provided on a silicon substrate and having a MOSFET and a capacitor. An insulative layer is formed on the substrate, and a first polycrystalline silicon layer is formed on this insulative layer. These layers are simultaneously subjected to etching and define a contact hole which penetrates them to come in contact with the surface of the source. A second polycrystalline silicon layer is formed on the first polycrystalline silicon layer to uniformly cover the inner wall of the contact hole and that surface portion of the source which is exposed through the contact hole. The first and second silicon layers are simultaneously subjected to patterning to provide the lower electrode of the capacitor. After a capacitor insulation layer is formed on the second polycrystalline silicon layer, a third polycrystalline silicon layer is formed on the capacitor insulation layer so as to bury a recess of the second polycrystalline silicon layer. The third silicon layer constitutes the upper electrode of the capacitor.

Claims26

Dependent claims

A semiconductor memory device with a stacked capacitor cell structure, comprising:

a semiconductive substrate;
a memory cell, provided on said substrate and having a transistor, a capacitor and an insulative layer formed on said substrate so as to have an opening, and positioned between said transistor and said capacitor,
said transistor having first and second semiconductive active layers formed in said substrate and an electrode layer insulatively deposited above said substrate,
the improvement where said capacitor comprises:
(a) a first conductive layer formed on said insulative layer and around said opening, said first conductive layer having an opening formed continuous with said opening of said insulative layer to thereby define a contact hole coupled to one of said active layers;
(b) a second conductive layer formed on said first conductive layer in such a way as to cover an inner wall of said contact hole and that surface portion of one of said active layers which is exposed through said contact hole, said second conductive layer having a recess corresponding to said contact hole, said first and second conductive layers constituting a first electrode of said capacitor;
(c) an insulative thin film formed on said second conductive layer and serving as a capacitor insulative layer;
and
(d) a third conductive layer formed on said insulative thin film so as to cover said recess of said second conductive layer, said third conductive layer constituting a second electrode of said capacitor.

6 more elements

A method of manufacturing a semiconductor memory device having a stacked capacitor cell structure, said method comprising the steps of:

(a) forming a transistor of a memory cell on a semiconductor substrate, said transistor having first and second semiconductive active layers formed in said substrate and an electrode layer insulatively disposed above said substrate;
(b) forming an insulative layer so as to cover said transistor;
(c) forming a first conductive layer on said insulative layer;
(d) forming an opening in said insulative layer and said first conductive layer by an etching process in such a way as to partially expose a surface of one of said active layers;
(e) forming a second conductive layer on said first conductive layer in such a way as to cover an inner wall of said opening and said exposed surface portion of said one of said active layers, said second conductive layer having a recess corresponding to a contact hole;
(f) subjecting said first and second conductive layers to patterning to thereby define a first electrode of a capacitor;
(g) forming an insulative thin film on said second conductive layer and serving as a capacitor insulative layer;
and
(h) forming a third conductive layer on said insulative thin film in such a way as to cover said recess of said second conductive layer, said third conductive layer constituting a second electrode of said capacitor to thereby provide a capacitor of said memory cell.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device with stacked capacitor structure and the manufacturing method thereof

Life of this patent

Semiconductor memory device with stacked capacitor structure and the manufacturing method thereof

Life of this patent

Abstract

Claims26