Floating gate memory circuit and apparatus

A memory circuit comprising

• a plurality of write lines, read lines, power supply lines, and row select lines,
• a plurality of memory cells connected to said lines, each of said cells comprising
• a memory device which includes
• source, drain and control gate electrode means,
• a semiconductor channel for conducting carriers from said source to said drain means, and
• a semiconductor heterostructure disposed between said channel and control gate means, said heterostructure including a floating gate potential well for confining carriers in a region sufficiently close to said channel to at least partially deplete it and further including a graded bandgap injector region for controlling the flow of carriers between said control gate means and said potential well,
• said source means being connected to a source of reference potential,
• a first FET having its channel connected between said gate means of said memory device and one of said write lines,
• a second FET having its channel connected between said drain means of said memory device and one of said read lines and one of said power supply lines,
• the gates of said FETs being connected to one of said row select lines, and
• circuit means for maintaining the voltage on said supply line essentially constant.