System for providing notification of impending FIFO overruns and underruns

Abstract

The fill or empty level of a FIFO is detected and compared to a first request level for the direct memory access controller or the coprocessor. When the fill or empty level exceeds the first request level, notification to the DMA or the coprocessor is generated. The fill or empty level is also compared to a second request level and when such level exceeds second request level, notification to the CPU is generated. Thus, in most cases, the DMA or coprocessor is able to obtain control of the bus before the request level for CPU interrupt is reached, thereby preventing wasteful CPU intervention as well as FIFO overruns and underruns. In case the DMA or coprocessor is unable to obtain control of the bus before the request level for CPU interrupt is reached, CPU intervention is available as a last resort.

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