US 4,937,697 A · Semiconductor device protection circuit

Abstract

Semiconductor device protection circuit (10) provides increased power dissipation (current) limits for FET (11) when lower FET temperatures exist. The FET drain to source voltage (V.sub.DS) is monitored to provide a current sense signal (54). When the current sense signal exceeds a predetermined reference limit signal (V.sub.REF,55), a control circuit (23, 32) reduces current (power dissipation) in the FET. Circuitry (24) provides the reference limit signal (V.sub.REF) with a predetermined temperature variation as a function of the sensed temperature of the FET whereby for low device temperatures higher power dissipation (current) limits for the FET are provided. An additional control circuit (21, 30) provides short circuit overcurrent protection by reducing current in the FET when sensed FET current exceeds a predetermined limit. A delay circuit (39) inhibits operation of at least the control circuit (20, 32) until a predetermined time (t.sub.1) after the FET is turned on.

Claims14

Dependent claims

A semiconductor device protection circuit comprising:

semiconductor device for receiving at least one control signal and, in response thereto, selectively passing current therethrough;
sense means coupled to said device for developing a power dissipation sense signal having a magnitude indicative of the power dissipated by said device when said device is on;
first control means for receiving said power dissipation sense signal and a first predetermined reference limit signal and modifying said control signal to reduce power dissipation in said device in response to the magnitude of said sense signal exceeding the magnitude of said reference limit signal by a predetermined amount;
and
means for developing said predetermined reference limit signal such that said reference limit signal varies in accordance with a sensed temperature signal and has a magnitude varying in accordance with the temperature of said device, wherein the reference limit signal is varied so as to allow a higher maximum power dissipation by said device at lower device temperatures than at higher device temperatures before the control means modifies operation of said device.

2 more elements

A semiconductor device protection circuit comprising:

semiconductor device for receiving at least one control signal and, in response thereto, selectively passing current therethrough;
sense means coupled to said device for developing a current sense signal having a magnitude indicative of the current passed through said device when said device is on;
first control means for receiving said current sense signal and a first predetermined reference limit signal and modifying said control signal to reduce current through said device in response to the magnitude of said sense signal exceeding the magnitude of said reference limit signal by a predetermined amount;
and
means for developing said predetermined referenced limit signal such that said reference limit signal varies in accordance with a sensed temperature signal and has a magnitude varying in accordance with the temperature of said device, wherein the reference limit signal is varied so as to allow a higher maximum current through said device at lower device temperatures than at higher device temperatures before the control means modifies operation of said device.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor device protection circuit

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Semiconductor device protection circuit

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Abstract

Claims14