Floating gate memory with sidewall tunnelling area

An electrically alterable, nonvolatile, flowing gate type memory device, comprising a substrate (2) of semiconductor material having a channel region (9) of a first type of conductivity between a first (10) and a second region (7) of a second type of conductivity, formed at the surface of said semiconductor substrate, said channel region providing a region within the semiconductor capable of passing an electric current between said first and said second region, a first level of patterned conducting material, constituting said floating gate (1), extending over said channel region (9), substantially between said first (10) and said second region (7) and electrically insulated by means of a first layer (3) of dielectric material from said semiconductor substrate and by means of a second layer (4) of dielectric material from a second level of patterned conducting material, constituting a control gate (5), overlying said floating gate (1) and which further includes

• a tunnel area defined on the surface of one of said first (10) and second (7) regions of the semiconductor substrate, said tunnel area being bordered on one side by the base of a portion of the length of a side wall of said floating gate (1) and being covered with a third layer (8) of dielectric material thinner than said first layer (3) of dielectric material;
• a tapered, lateral, seamlike appendix (1b) of conducting material juxtaposed along said portion of the length of the side wall of said floating gate (1), the base of said juxtaposed, tapered, lateral, seamlike appendix (1b) of conducting material abutting on the surface of said third layer (8) of dielectric material covering said tunnel area;
• said seamlike appendix (1b) being electrically connected to said patterned first level of conducting material constituting said floating gate (1).