High resolution event occurrance time counter

A high resolution event occurrence time counter, which comprises:

• free running counter means, the counter means being responsive to a clock signal and providing count data which varies in response to the clock signal, the clock signal being periodic, each period of the clock signal having a first half period and a second half period;
• first register means for storing the count data of the free running counter means, the first register means being responsive to the clock signal and storing the count data in response thereto, the first register means providing first register data representative of the count data stored therein;
• second register means for storing the first register data of the first register means, the second register means providing first time of arrival data representative of the first register data stored therein;
• third register means for storing the count data of the free running counter, the third register means providing second time of arrival data representative of the count data stored therein;
• clock edge encoder means for determining whether an event occurred during one of the first half period and the second half period of the clock signal, the clock edge encoder means providing a first sync signal when the event occurred during the first half period, and a second sync signal when the event occurred during the second half period;
• the second register means being responsive to the first sync signal and storing the first register data in response thereto;
• the third register means being responsive to the second sync signal and storing the count data in response thereto;
• wherein at least the first time of arrival data is provided as output data of the event occurrence time counter when at least the first sync signal is provided by the clock edge encoder means, and at least the second time of arrival data is provided as output data when at least the second sync signal is provided by the clock edge encoder means.