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US 4,908,691 AGranted
Selective epitaxial growth structure and isolation
AssigneeInternational Business Machines Corporation
InventorsVictor J. Silvestri, Paul J. Tsang
Life of this patent
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Abstract
A novel method of employing selective epitaxial growth, in which interdevice isolation is intrinsically formed. Problems stemming from formation of all active device elements within selective epitaxial growth regions are addressed. Additionally, there is shown a novel transistor array formed according to the method of the invention.
Claims15
An array of integrated circuit devices, comprising:
- a monocrystalline silicon substrate having an upper and lower portion, said upper portion being doped in accordance with types of devices being formed, said lower portion forming subcollectors for said devices, said substrate having a plurality of trenches formed therein, said trenches extending through said upper portion into said lower portion;
- an oxide layer formed in each of said trenches, each said oxide layer having an opening to said lower portion of said substrate;
- epitaxial silicon filling each of said trenches;
- a first plurality of active device elements formed in said epitaxial silicon, said first plurality of active device elements being appropriately doped so as to form a plurality of P-N junctions between adjacent ones of said first plurality of active device elements, said P-N junctions between said active device elements having equal areas, and being vertically aligned with each said opening, a first plurality of devices thereby being formed;
- and
- a second plurality of active device elements formed in said upper portion of said substrate between consecutive ones of said trenches, said second plurality of active device elements forming a second plurality of devices complementary in type to said first plurality of devices.
3 more elements
An array of bipolar metal oxide semiconductor (MOS) integrated circuit devices, comprising:
- a monocrystalline silicon substrate having an upper and lower portion, said upper portion being doped in accordance with types of devices being formed, said lower portion forming subcollectors for said devices, said substrate having a plurality of trenches formed therein, said trenches extending through said upper portion into said lower portion;
- an oxide layer formed in each of said trenches, each said oxide layer having an opening to said lower portion of said substrate;
- epitaxial silicon filling each of said trenches;
- a first plurality of active device elements formed in said epitaxial silicon, said first plurality of active device elements being appropriately doped so as to form a plurality of P-N junctions between adjacent ones of said first plurality of active device elements, said P-N junctions between said active device elements having equal areas, and being vertically aligned with each said opening, a first plurality of bipolar MOS transistors thereby being formed;
- and
- a second plurality of active device elements formed in said upper portion of said substrate between consecutive ones of said trenches, said second plurality of active device elements forming a second plurality of devices complementary in type to said first plurality of devices.
3 more elements
An array of integrated circuit devices, comprising:
- a gallium arsenide substrate having an upper and lower portion, said upper portion being doped in accordance with types of devices being formed, said lower portion forming subcollectors for said devices, said substrate having a plurality of trenches formed therein, said trenches extending through said upper portion into said lower portion;
- an oxide layer formed in each of said trenches, each said oxide layer having an opening to said lower portion of said substrate;
- epitaxial gallium arsenide filling each of said trenches;
- a first plurality of active device elements formed in said epitaxial gallium arsenide, said first plurality of active device elements being appropriately doped so as to form a plurality of P-N junctions between adjacent ones of said first plurality of active device elements, said P-N junctions between said active device elements having equal areas, and being vertically aligned with each said opening, a first plurality of devices thereby being formed;
- and
- a second plurality of active device elements formed in said upper portion of said substrate between consecutive ones of said trenches, said second plurality of active device elements forming a second plurality of devices complementary in type to said first plurality of devices.
3 more elements
Dependencies are inferred from the claim text.