Semiconductor integrated circuit device with high reliability wiring layers
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsMasayuki Hata, Hiromasa Nakagawa
Life of this patent
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Abstract
A semiconductor integrated circuit device includes a semiconductor substrate and a wiring layer formed on the substrate. An output buffer transistor is provided with its gate formed along the direction of the wiring. The resulting device has improved area efficiency and is less susceptible to wiring element slide without requiring slits to be formed in the wiring structure--and thus also has lower current density.
Claims12
A semiconductor integrated circuit device including a semiconductor substrate 10, an insulating layer 12 formed thereon and having a plurality of contact holes 16 and bulk contact holes 17 and a wiring portion 7,8 formed on said insulating layer 12 and extending in a direction, comprising at least a MOS field effect transistor having a source 18 and a drain 19 both formed in said substrate 10 and a gate 5 formed between said substrate and said wiring portion and extending substantially in parallel with the direction of said wiring portion.
A semiconductor integrated circuit structure of the type including a transistor having a source, a drain and a gate, said structure including:
- a semiconductor substrate;
- an insulating layer disposed on said substrate, said insulating layer having at least one contact hole (16) and at least one bulk contact hole (17) therethrough;
- and
- a wiring structure disposed on said insulating layer, said wiring structure having an elongated portion extending in a first direction, said wiring structure including a wiring portion means, coupled to said transistor gate and disposed between said substrate and said wiring structure and extending substantially parallel to said first direction, for preventing sliding of said wiring structure.
A semiconductor integrated circuit structure including:
- a semiconductor substrate;
- a transistor source region disposed in said substrate;
- a transistor drain region disposed in said substrate;
- a transistor gate structure operatively coupled to said source region and said drain region;
- an insulating layer disposed on said substrate said insulating layer having at least one contact hole means (16) and at least one bulk contact hole means (17) therethrough, said contact hole means and said bulk contact hole means each for permitting electrical contact to be established between a wiring structure and said substrate;
- said wiring structure disposed on said insulating layer, said wiring structure having an elongated portion extending in a first direction;
- wherein said transistor gate structure comprises means disposed between said substrate and said wiring structure and extending substantially parallel to said first direction, for preventing sliding of said wiring structure.
Dependencies are inferred from the claim text.