Process for making metal-polysilicon double-layered gate
AssigneeIndustrial Technology Research Institute
InventorNeng-Wei Wu
Life of this patent
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Abstract
A process for reducing gate sheet resistance in VSLI devices employs planarization and metal refilling to produce a gate of layers of polysilicon and pure metal. The polysilicon underlayer maintains the characteristics of a polysilicon gate and the metal layer reduces the gate sheet resistance. The process includes the etching back of the planarized dielectric (6) to expose the top surface of the polysilicon gate (3), the etching of the polysilicon to form a groove, and the filling of the groove with a metal, e.g. W, by selective or blanket CVD.
Claims6
A process for forming a double-layered gate interconnect on a substrate, comprising:
- (1) forming a recess isolation structure on the substrate;
- (2) forming a polysilicon gate interconnect layer on the substrate;
- (3) forming source and drain regions on the substrate;
- (4) depositing a planarized dielectric layer on the gate interconnect and the source and drain regions;
- (5) etching back the planarized dielectric layer to the expose top surface of the polysilicon gate interconnect layer;
- (6) partially etching the polysilicon gate interconnect to form a groove;
- and
- (7) filling the groove with a metal gate interconnect layer to abut the polysilicon gate interconnect layer to form a double-layered gate interconnect.
Dependencies are inferred from the claim text.