Semiconductor memory device

A semiconductor memory device including a plurality of memory cells, each of said memory cells comprising:

• a semiconductor substrate which is heavily doped with an impurity of a first conductivity type and having a major surface and a primary cavity formed in said major surface, said primary cavity having side and bottom portions;
• a storage capacitor having a first electrode formed by said side and bottom wall portions defining said primary cavity, a first thin dielectric film covering the side and bottom wall portions and having a geometry substantially dictated by the configuration of the side and bottom wall portions to define a secondary cavity, and a second electrode filling the secondary cavity and projecting from the major surface of the semiconductor substrate, said first electrode being heavily doped with said impurity of said first conductivity type, and said second electrode being formed of a semiconductor material which is doped with a second, opposite conductivity type;
• a thick insulating layer convering the major surface of the semiconductor substrate and having formed therein a first opening substantially aligned with the secondary cavity to allow the second electrode to extend beyond the surface of the thick insulating layer, said thick insulating layer having a flat surface extending along an upper surface thereof;
• and
• a switching transistor provided on the thick insulating layer and comprising an epitaxial semiconductor layer formed in part on said thick insulating layer and electrically coupled to said second electrode, part of said semiconductor layer constituting source and drain regions and a channel region which separates said source and drain regions from each other, each of said source and drain regions being doped with an impurity of said second conductivity type, boundaries between said channel region and said source and drain regions being located on said flat surface, said switching transistor further comprising a second thin dielectric film formed on the channel region, and a gate electrode formed on the second thin dielectric film, one of the source and drain regions being connected to the second electrode of the storage capacitor, said thick insulating layer having a second opening through which said channel region extends to said major surface of said semiconductor substrate.