Planar famos transistor with trench isolation

A non-volatile memory cell array comprising:

• a semiconductor substrate;
• a plurality of doped bit line regions formed in said substrate;
• a plurality of floating gates overlying said substrate, each having a top surface, and each of said floating gates disposed between a pair of bit line regions and defining a channel region in said substrate lying under said floating gate and between said bit line regions;
• a plurality of dielectric structures, each disposed over one of said bit line regions and having a top surface substantially even with the top surfaces of said floating gates;
• a plurality of control gages each overlying a plurality of floating gates and overlying a plurality of dielectric structures and bit line regions therebelow;
• and
• a plurality of trench isolation regions each disposed between adjacent ones of said floating gates disposed between the same pair of bit line regions, and between adjacent ones of said dielectric structures overlying said pair of bit line regions, said trench isolation regions extending into said substrate substantially below the surface of said channel regions.