US 4,904,615 AGranted

Method of making a read only memory device

AssigneesHitachi, Ltd., Hitachi Microcomputer Engineering Ltd.

InventorsKousuke Okuyama, Ken Uchida, Kouichi Kusuyama, Satoshi Meguro, Hisao Katto, Kazuhiro Komori

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Abstract

Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced. Furthermore, there is disclosed a memory structure of a semiconductor memory device suitable for a higher degree of integration through an arrangement of gate electrodes of multiple layers.

A manufacturing method of a semiconductor memory device having a vertical-type mask ROM with first-layer and second-layer gate electrodes, in which the second-layer gate electrodes are formed from a second conductive layer, between adjacent ones of the first-layer gate electrodes, which first-layer gate electrodes are formed from a first conductive layer and are disposed at a predetermined interval in a direction of gate length of the first-layer gate electrodes, comprising the steps of:

introducing an impurity of first conductivity type into a principal surface of a semiconductor substrate;
forming the first-layer gate electrodes at the predetermined interval on the principal surface of the semiconductor substrate;
forming a first masking layer having openings at positions corresponding to said predetermined interval between said ones of first-layer gate electrodes, ends of said masking layer being disposed on said first-layer gate electrodes;
implanting an impurity of a second conductivity type to write information into the principal surface of the semiconductor substrate between the first-layer gate electrodes by using the first-layer gate electrodes as a mask so as to write first information, said first-layer gate electrodes used as said mask being disposed in said openings of said first masking layer;
removing said first masking layer;
forming a second masking layer having openings at positions corresponding to particular ones of said first-layer gate electrodes, ends of said second masking layer being disposed between said ones of said first-layer gate electrodes;
further implanting an impurity of the second conductivity type to write information into the principal surface of the substrate beneath said first-layer gate electrodes, through the first-layer gate electrodes disposed in said openings of said second masking layer, thereby writing second information;
and
forming the second layer gate electrodes on the principal surface of the substrate in which said first information has been written.

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Abstract

Claims13