Enhanced tab package
AssigneeInternational Business Machines Corporation
InventorsRichard F. Frankeny, James M. Rakes
Life of this patent
Estimating the term…
Abstract
Improved tape automated bonding (TAB) packaging technology is disclosed having particular utility with semiconductor integrated circuit chips having high gate count and I/O requirements, utilizing a polymer layer of the package to support decoupling capacitor(s) mounted across power and ground leads connecting the chip and internal planes of a printed circuit board to which the TAB package is attached.
Claims5
An improved semiconductor device TAB package for electrical connection to printed circuit substrate, having plural conductive planes comprising:
- a planar flexible insulating member;
- a pattern of conductive leads, including power and ground leads, formed on said flexible insulating member;
- at least a decoupling capacitor across adjacent ones of said power and ground leads;
- means for connecting said semiconductor device to first ends of at leaast some conductive leads in said pattern, said means comprising apertures in said flexible insulating member adapted for permitting direct attachment of said power and ground leads to interior sites on a surface of said semiconductor device or on peripheral edges of said device;
- and
- means for selectively connecting opposite ends of some of said conductive leads to surface circuitry and internal conductive planes of said circuit substrate.
An improved tape automated bonding package for a semiconductor device comprising:
- a polymer layer:
- a pattern of electrical leads formed on a surface of said polymer layer including signal, power and ground lines adapted for connection to said semiconductor and to circuitry on a printed circuit substrate;
- apertures in said polymer layer adjacent to a surface of said semiconductor device, through which power and ground connections to said device are made;
- and
- at least one decoupling capacitor surface mounted across said power and ground lines on said polymer layer.
A semiconductor device TAB package adapted for electrically connecting leads from a semiconductor device selectively to conductors on any plane of a multiplane printed circuit substrate comprising:
- a planar flexible insulating member, having at least an aperture substantially smaller than said semiconductor device;
- a plurality of conductive leads, including signal, power and ground leads, provided in a predetermined pattern about said aperture on said planar flexible member;
- said pattern including at least one power lead and at least one ground lead passing through said aperture substantially smaller than said semiconductor device;
- means for connecting said at least ones of said power and ground leads passing said aperture to said semiconductor device, through said aperture, at sites interior from peripheral edges of said semiconductor device;
- and
- at least a decoupling capacitor mounted across said at least ones of said power and ground leads in close proximity to said substantially smaller aperture.
A semiconductor chip device TAB package adapted for electrically connecting leads from said semiconductor chip device to any conductive plane in a printed circuit substrate having plural conductive planes comprising:
- a planar flexible insulating member;
- a pattern of conductive leads, inculding power and ground leads, formed on a surface said flexible insulating member,
- said pattern including having first ends of at least some of said conductive leads terminating at the edges of an area having a size and shape substantially corresponding to that of said semiconductor chip device, and
- at least one ground lead and at least one power lead traversing said area;
- a plurality of apertures formed in said flexible insulating member in said area adjacent to said first ends of at least some conductive leads and in said area adjacent said at least one power leads and at least one ground lead;
- means for connecting said first ends of at least some of said conductive leads to said semiconductor device through apertures located at sites corresponding to peripheral edges of said semiconductor device;
- means for electrically connecting said at least one power lead and at least one ground lead to said semiconductor device at sites on said semiconductor device interior from edges of said semiconductor device through at least one aperture adjacent said at least one power lead and at least one ground lead;
- and
- at least a decoupling capacitor mounted across said at least one power lead and at least one ground lead in close proximity to one of said apertures.
Dependencies are inferred from the claim text.