MESFET sram with power saving current-limiting transistors

A static random access memory cell implemented with metal Schottky field-effect transistors, said cell adapted for connection to a source of bias voltage and a reference potential, said cell responsive to a word-line signal and complimentary bit-line signals for storing complimentary voltage levels, said cell comprising:

• first and second branches, each of said branches including
• a depletion mode current limiting transistor having a drain connected to a first circuit node,
• a depletion mode load transistor having a drain connected to the source of said current limiting transistor and a source and gate connected to a second circuit node,
• an enhancement mode active transistor having a drain connected to said second circuit node and a source connected to a third circuit node,
• an enhancement mode access transistor having a source connected to said second circuit node and a gate connected to the gate of said current limiting transistor,
• the commonly connected gates of said current limiting transistor and said access transistor adapted to receive said word-line signal,
• the drain of said access transistor adapted to receive a bit-line signal,
• said first circuit node adapted for connection to said source of bias voltage, and
• said third circuit node adapted for connection to said circuit reference potential;
• and
• said first and second branches cross-connected between said second nodes and the gates of said active transistors.