An integrated circuit semiconductor structure providing a first vertical bipolar transistor and a second lateral bipolar transistor connected in a thyristor configuration with a JFET, said integrated circuit semiconductor structure comprising:
- semiconductor substrate means including a semiconductor body portion of a first conductivity type and a semiconductor layer portion of a second conductivity type disposed on said semiconductor body portion, a PN junction defined between said semiconductor body portion of said first conductivity type and said semiconductor layer portion of said second conductivity type electrically isolating said semiconductor layer portion of said second conductivity type from said semiconductor body portion of said first conductivity type;
- a first dopant region of said first conductivity type disposed in said semiconductor layer portion of said second conductivity type and opening onto the surface thereof;
- a second dopant region of said second conductivity type disposed within said first dopant region of said first conductivity type and opening onto the surface of said first dopant region;
- a third dopant region of said second conductivity type disposed in said semiconductor layer portion of said second conductivity type and having a higher dopant concentration in relation thereto, said third dopant region of said second conductivity type onto the surface of said semiconductor layer portion of said second conductivity type and disposed in laterally spaced relationship with respect to said first dopant region of said first conductivity type;
- a fourth dopant region of said first conductivity type disposed within said third dopant region of said second conductivity type and opening onto the surface of said third dopant region;
- said first dopant region and said second dopant region defining the base region and the emitter region respectively with the underlying area of said semiconductor layer portion defining the collector region of said first vertical bipolar transistor;
- said base region and said collector region of said first vertical bipolar transistor respectively defining a gate and a channel of said JFET;
- said fourth dopant region of said first conductivity type cooperating with said semiconductor layer portion of said second conductivity type and said first dopant region of said first conductivity type in respectively defining the emitter, base and collector regions of said second lateral bipolar transistor connected in the thyristor configuration to said first vertical bipolar transistor through said JFET;
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- set JFET enabling said first vertical bipolar transistor to withstand a higher voltage signal by achieving a pinch-off condition before the onset of voltage breakdown between the collector and emitter regions of said first vertical bipolar transistor, and said second lateral bipolar transistor having the capability of achieving a higher withstand voltage due to the prevention of surface inversion by said third dopant region of said second conductivity type.