FIFO with almost full/almost empty flag
OwnerGerard A. Kreifelsinventor
Life of this patent
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OwnerGerard A. Kreifelsinventor
Estimating the term…
An almost full flag for a FIFO includes first and second counters for determining the proximity of the Read and Write pointers in the FIFO. A compare circuit is provided for comparing the output of the counters to determine when the count values are separated by a predetermined value. When the separation is equal to the predetermined value, the output of the comparitor goes low. A half flag is set when a Write operation occurs and the difference value between the Read and Write pointers increases. The set operation is performed in response to the presence of the compare signal at a low logic state at the time that the Write operation occurs, thus eliminating any delays in generating a transition in the compare circuit. The flag is reset when the compare signal is at the low logic state. Blanking circuitry is provided for blanking the reset operation when a Read operation occurs and the output of the comparator makes a transition from the first logic state to the second logic state. The blanking operation occurs for a predetermined duration of time to allow the counter to settle before performing the reset operation.
An almost full flag for a FIFO, comprising:
An almost full flag for a FIFO, comprising:
A method for indicating an almost full condition for a FIFO, comprising:
Dependencies are inferred from the claim text.