US 4,884,115 A · Basic cell for a gate array arrangement in CMOS Technology

Abstract

A gate array arrangement provides basic cells in a core region, with logic functions or storage functions being realized by wiring these basic cells. The basic cells are composed of six or seven transistors in CMOS technology, with three p-channel transistors (TR1) in a a first region (BE1) and three n-channel transistors (TR2) in a second region (BE2), with the terminals (GTA) of the gate electrodes (GT1, GT2) of the transistors being arranged between these two regions (BE1, BE2). A further transistor (TR3) that has a smaller channel width than the remaining transistors (TR1, TR2) is arranged outside of the region (BE2) for the n-channel transistors (TR2). The gate electrode (GT3) of the further transistor lies parallel to the electrodes (GT2) connected to the gates of the n-channel transistors (TR2) but is shorter. The terminal (GTB) of the gate electrode (GT3) of the further transistor (TR3) faces toward the line for the supply voltage (VSS). The terminals (GTA) of the gate electrodes of the n-channel and p-channel transistors lie next to one another and can thus be connected to one another by the shortest possible path, and adequate space is available over the regions (BE1, BE2) to conduct wiring lines above the cell.

Claims12

Dependent claims

A basic cell for a gate array arrangement in CMOS technology, including a first region containing a plurality of first transistors of one conductivity type connected in series, and a second region having an identical plurality of second transistors of the opposite conductivity from said one type connected in series, each of said transistors having a gate electrode, a drain electrode, and a source electrode, a plurality of first connecting lines respectively connected to said gate electrodes of said first transistors in said first region and a plurality of second connecting lines respectively connected to said gate electrodes of said second transistors in said second region, said first and second connecting lines being arranged in parallel with each other,

(a) said first and second lines being connected respectively to a plurality of gate electrode contacts located between said first and second regions, said electrode contacts being located at different staggered positions along a direction parallel with said lines, one line of each of said first and second lines being connected in common to a single one of said gate electrode contacts,
(b) a first supply conductor adapted to be connected to a first supply voltage positioned outside said first connecting lines at the outer edge of said first region proceeding in a direction parallel to said first series connected transistors, and
(c) a second supply conductor adapted to be connected to a second supply voltage positioned outside said second connecting lines at the outer edge of said second region proceeding a direction parallel to said second series connected transistors.

A basic cell for a gate array arrangement constructed in CMOS technology, comprising, in combination:

a plurality of series-connected first transistors of one conductivity type, each having a drain electrode, a gate electrode and a source electrode, said first transistors being arranged successively in parallel with each other in a first region, an equal number of series-connected second transistors of the opposite conductivity from said one type, each having a source electrode, a gate electrode and a drain electrode, said second transistors being arranged successively in parallel to each other in a second region spaced from said first region, a first plurality of connecting lines interconnected with respective gate electrodes of said first transistors, a second plurality of connecting lines interconnected with respective gate electrodes of said second transistors, said first and second connecting lines being parallel to each other, a first gate contact connected to one of said first connecting lines, a second gate contact connected to one of said second connecting lines, said first and second gate contacts located in the space between said first and second regions and offset from each other whereby said first gate contact is closer than said second gate contact to said first region and said second gate contact is closer than said first gate contact to said second region,
a first supply line adapted to be connected to a first supply voltage arranged at the outer edge of said first region and aligned in parallel to the direction of the series-connected first transistors,
a second supply line for a second supply potential arranged at the outer edge of said second region, aligned in parallel to the direction of the series-connected second transistors,
a substrate contact arranged adjacent to one side of said first region and aligned in parallel with the said first transistors, a well contact arranged adjacent to one side of said second region aligned in parallel to said second transistors,
a third transistor of said opposite conductivity type adjacent to one side of said second region, said third transistor having drain, source and gate electrodes, the gate electrode of said third transistor being located in parallel to said second connecting lines but shorter than said second connecting lines, and including a third gate contact located between said third transistor and said well contact, said third gate contact being connected to the gate electrode of said third transistor.

2 more elements

Dependencies are inferred from the claim text.

Basic cell for a gate array arrangement in CMOS Technology

Life of this patent

Basic cell for a gate array arrangement in CMOS Technology

Life of this patent

Abstract

Claims12