Back to results
US 4,876,466 AGranted
Programmable logic array having a changeable logic structure
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHarufusa Kondou, Hiroshi Kuranaga
Life of this patent
Estimating the term…
Abstract
Programmable Logic Array PLA) cells are arranged at intersections of input lines and output lines of the array. Particular PLA cells to be programmed are arbitrarily selected by word line and bit line decoders. Switches for programming the PLA cells to implement a desired logic function are controlled by data stored in a random access memory whereby programming of the PLA can be changed arbitrarily and during operation of a system including the PLA.
Claims13
A programmable logic array (PLA) comprising:
- a plurality of input signal lines each including a first input line for directly transmitting an input signal and a second input line for transmitting an inverted input signal;
- a plurality of output signal lines crossing said input signal lines;
- a plurality of programmable logic array cells at intersections of said plurality of input signal lines and said plurality of output signal lines, said programmable logic array cells forming an AND plane, each of said cells being programmable and commonly provided to a pair of said first input signal lines and said second input signal lines;
- and
- addressing means for selecting particular ones of said programmable logic array cells, wherein each said programmable logic array cell comprises
- (a) a random access memory for storing external data when selected by said addressing means, said memory being rewritable during operation of said PLA while carrying out a predetermined logic function for changing said function,
- (b) switching means which are opened or closed, selectively, by outputs of said memory means, and
- (c) PLA programming devices controlled by said switching means and connected to corresponding ones of said input signal lines and said output signal lines;
- wherein said PLA is alterably programmable by data stored in said memory means.
6 more elements
A programmable logic array (PLA), comprising:
- a plurality of input signal lines;
- a plurality of output signal lines crossing said input signal lines;
- a plurality of programmable logic array cells at intersections of said plurality of input signal lines and said plurality of output signal lines, each of which cell can be programmed;
- and
- addressing means for selecting particular ones of said programmable logic array cells, wherein each said programmable logic array cell comprises
- (a) a random access memory for storing external data when selectee by said addressing means, said memory being rewritable during operation of said PLA while carrying out a predetermined logic function for changing said function,
- (b) switching means which are opened or closed, selectively, by outputs of said memory means, and
- (c) PLA programming devices controlled by said switching means and connected to corresponding ones of said input signal lines and said output signal lines;
- wherein said PLA is alterably programmable by data stored in said memory means, and a microcomputer for reprogramming the PLA while the PLA is carrying out a predetermined logic function is provided;
- said microcomputer including an internal memory wherein said PLA is structured utilizing a portion of said internal memory.
7 more elements
A programmable logic array (PLA), comprising:
- a plurality of input signal lines;
- a plurality of output signal lines crossing said input signal lines;
- a plurality of programmable logic array cells at intersections of said plurality of input signal lines and said plurality of output signal lines, each of which cell can be programmed;
- and
- addressing means for selecting particular ones of said programmable logic array cells, wherein each said programmable logic array cell comprises
- (a) a random access memory for storing external data when selectee by said addressing means, said memory being rewritable during operation of said PLA while carrying out a predetermined logic function for changing said function,
- (b) switching means which are opened or closed, selectively, by outputs of said memory means, and
- (c) PLA programming devices controlled by said switching means and connected to corresponding ones of said input signal lines and said output signal lines;
- wherein said PLA is alterably programmable by data stored in said memory means, and a microcomputer for reprogramming the PLA while the PLA is carrying out a predetermined logic function is provided, said microcomputer including an internal memory wherein said PLA is structured utilizing a portion of said internal memory;
- a method of operating said PLA, including the steps of programming said random access memory for defining a predetermined logic function, operating said PLA for carrying out the predetermined function programmed in said random access memory, and, during said step of operating PLA, reprogramming said random access memory to define a different predetermined logic function.
7 more elements
Dependencies are inferred from the claim text.