Programmable resistance network

A method of manufacturing a programmable resistance network, comprising:

• depositing a film resistor layer comprising a compound of titanium and tungsten onto a substrate in accordance with a predetermined resistance pattern to form a resistor array, said array establishing an incremental resistance value for each resistor in the array;
• and
• depositing a conductive layer, according to a predetermined pattern, onto said substrate and over said resistor array to create a connector grid for forming terminals connected to said resistor array;
• wherein successively fusing said resistors by application of an increasing flow of electricity progressively increases total array value.

A programmable resistance network, comprising:

• a first elongate resistor array terminal;
• a second elongate resistor array terminal askew from said first terminal;
• and
• a plurality of parallel resistors connected as an array between said first and second terminals, each successive resistor having a progressively higher resistance value than that of preceding resistors, said resistors having the property of being selectively deletable by applying an increasing flow of electricity across said first and second terminals to progressively fuse successive array resistors.

An integrated circuit programmable resistance network, comprising:

• a first elongate resistor terminal;
• a plurality of elongate parallel film resistors of progressively increasing length, said resistors having a first end connected to, and substantially perpendicular to said first terminal, each resistor having a resistance value that is a function of its length;
• and
• a second elongate resistor terminal connected to said resistors at a second resistor end, said resistors having the property of being selectively deletable by applying an increasing flow of electricity across said first and second terminals to progressively fuse successive resistors.

In an integrated circuit including a semiconductor substrate and having a dual in-line pin (DIP) package, a monolithic programmable resistor network, including a plurality of independent resistor arrays, each resistor array comprising:

• a film resistor layer deposited onto said substrate, said resistor layer arranged to form a pattern of parallel resistive layer arranged to form a pattern of parallel resistive elements, each successive resistance element being of greater length and resistance value than that preceding it;
• and
• a conductive layer deposited onto said resistive layer, said conductive layer arranged to form a first resistor array terminal at one end of said parallel resistive elements and to form a second resistor array terminal at another end of said parallel resistive elements, said first and second resistor array terminals being connected to a first and second DIP package pin, respectively,
• wherein a selected flow of a programmable voltage provided across said first and second DIP package pins progressively fuses successive resistive elements in said resistor array and provides a progressively increasing total resistor array resistance value.

A method of manufacturing a programmable resistance network, comprising:

• depositing a film resistor layer onto a substrate in accordance with a predetermined resistance pattern to form a resistor array, said array establishing an incremental resistance value for each resistor in the array;
• and
• depositing an aluminum layer, according to a predetermined pattern, onto said substrate and over said resistor array to create a connector grid for forming terminals connected to said resistor array;
• wherein successively fusing said resistors by application of an increasing flow of electricity progressively increases total array value.

A method of manufacturing a programmable resistance network comprising:

• depositing a film resistor layer onto a substrate in accordance with a predetermined resistance pattern to form a resistor array, said array establishing an incremental resistance value for each resistor in the array;
• and
• depositing a conductive layer, according to a predetermined pattern, onto said substrate and over said resistor array to create a connector grid for forming terminals connected to said resistor array;
• wherein successively fusing said resistor by application of an increasing flow of electricity progressively increases total array value,
• said step of depositing including the step of varying the incremental length of successive resistive elements by forming said conductive layer with a selected conductor contour to progressively increase total resistor array resistance value according to a selected incremental progression as successive resistive elements are fused.