CMOS binary up/down counter
AssigneeRaytheon Company
InventorEdward T. Lewis
Life of this patent
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Abstract
A high speed CMOS binary up/down counter having a 200 MHZ clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. The counter performs in an up-count mode or a down-count mode in accordance with the state of a mode select signal. Each stage of the 4-bit counting section comprises a propagate/kill/generate gate for determining the status of a carry signal to a next stage, except the last stage of a 4-bit section, which does not require such a gate because it is coupled to a carry-forward generator along with the outputs from the other preceeding stages in the section. Each 4-bit section performs the counting function through a successive process of modulo-two sums of a lower order carry and the current state of a counter stage without the need for cumbersome gating structures.
Claims24
A binary up/down counter having a plurality of sequentially coupled stages, each of said stages comprising:
- means for storing a bit of a binary count, said storing means having a data input, a clock input, a first output providing said bit of the binary count and a second output providing a complement signal of said first output;
- means having an output coupled to said data input of said storing means for performing a modulo-two sum of a lower order carry signal and said first output or said second output of said storing means in accordance with an up/down mode selection signal;
- means coupled to said up/down mode selection signal and said lower order carry signal for determining whether to propagate/kill or propagate/generate a higher order carry signal in accordance with the state of said up/down mode selection signal and said first output or said second output of said storing means in accordance with the state of said up/down mode selection signal;
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- means coupled to said first output and said second output of said storing means for selecting whether said first output or said second output of said storing means is coupled to said modulo-two summing means and said higher order carry determining means in accordance with the state of said up/down mode selection signal.
A binary up/down counter having a plurality of concatenated sections comprising:
- a plurality of binary up/down counter stages in each of said sections for performing an up/down counting function in accordance with an up/down mode selection signal;
- means coupled between each pair of said counter sections for generating a carry-forward signal to an adjacent succeeding one of said sections;
- each of said binary counter stages comprising:
- (a) means for storing a bit of a binary count, said storing means having a data input, a clock input, a first output providing said bit of the binary count and a second output providing a complement signal of said first output;
- (b) means having an output coupled to said data input of said storing means for performing a modulo-two sum of a lower order carry signal and said first output or said second output of said storing means in accordance with said up/down mode selection signal;
- (c) means coupled to said up/down mode selection signal and said lower order carry signal for determining whether to propagate/kill or propagate/generate a higher order carry signal in accordance with the state of said mode up/down selection signal and said first output or said second output of said storing means in accordance with the state of said up/down mode selection signal;
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- (d) means coupled to said first output and said second output of said storing means for selecting whether said first output or said second output of said storing means is coupled to said modulo-two summing means and said higher order carry determining means in accordance with the state of said up/mode selection signal.
A method of performing binary up/down counting with a plurality of sequentially coupled stages comprising the steps of:
- storing a bit of binary count in a storing means having a data input, a clock input, a first output providing said bit of the binary count and a second output providing a complement signal of said first output;
- performing a modulo-two sum of a lower order carry signal and said first output or said second output of said storing means in accordance with an up/down mode selection signal, the result of said modulo-two sum being coupled to said input of said storing means;
- determining whether to propagate/kill or propagate/generate a higher order carry signal in accordance with the state of said up/down mode selection signal and said first output or said second output of said storing means in accordance with the state of said up/down mode selection signal;
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- selecting whether said first output or said second output of said storing means is coupled to a means for performing said modulo-two sum and said higher order carry determining means in accordance with the state of said up/down mode selection signal.
Dependencies are inferred from the claim text.