US 4,843,255 AGranted

Self-latching monostable circuit

AssigneeTektronix, Inc.

InventorCarlton Stuebing

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Abstract

A monostable circuit responsive conditionally to a circuit input signal for generating a circuit output signal having a pulse of a predetermined duration includes an AND gate having two input ports and an output port. ONe of the input ports is coupled to the circuit input signal and inverts that signal. The other of the input ports is coupled to the circuit output signal. A reset OR gate receives a reset signal and the output of the AND gate. When the reset signal is low, the reset OR gate outputs the output of the AND gate, thus enabling the curcuit. The output of the reset OR gate also goes to a ramp generator having a ramp capacitor, the charging current to which is provided by a current driver. The reference voltage for a comparator is provided by circuitry identical to that associated with the ramp capacitor except that an intermediate bias reference is applied to it. This bias reference is compensated for the effect temperature changes on the circuit. An external current source operating through a current mirror drives the capacitor current driver and the reference voltage. The outputs of the comparator and the reset OR gate are input into the output OR gate for producing the circuit output signal. When the output signal is low, or logic true, the AND gate is latched so that changes in the circuit input signal during this time period do not affect circuit operation.

Claims8

Dependent claims

A self-latching monostable circuit responsive conditionally to an input signal for generating an output signal having a pulse of a predetermined duration comprising:

AND gate means having two input ports including an inverting input on one of the input ports and an output port, one of said input ports being coupled to the input signal and the other of said input ports being coupled to said output signal;
OR gate means having two input ports for generating the output signal, one of said input ports of said OR gate means being coupled to said output of said AND gate means;
and
timing means having an input port coupled to said output port of said AND gate means, an output port coupled to the other of said input ports of said OR gate means, and a ramp capacitor coupled to the input port, the ramp capacitor being charged by a variable charging current, said timing means being responsive to the output of said AND gate means for changing the signal at said output port of said timing means from a first logic state to second logic state a predetermined period of time after the output of said AND gate means changes from a first logic state to a second logic state, said predetermined period of time being variable, whereby the output signal has a pulse of a predetermined width beginning when the input signal changes from a first to a second logic state while preventing further changes in the input signal from affecting the output signal during the predetermined duration, the output signal being latched in a predetermined logic state for the predetermined duration.

1 more element

Dependencies are inferred from the claim text.