Data alignment system for random and block transfers of embedded subarrays of an array onto a system bus
AssigneeSaxpy Computer Corporation
InventorRobert L. Papenberg
Life of this patent
Estimating the term…
Abstract
An alignment system for transferring only system words of a subarray embedded in an array in system memory between system memory and a buffer memory. The alignment system utilizes a parallel bus that transfers W system words per cycle and selects only subarray words for transfer between the system memory and the buffer. Additionally, a sequencer schedules and executes combinations of random and block accesses to mamximize bandwidth.
Claims7
In a data transfer apparatus including a system memory (SMEM) having its storage elements organized into wide words (WW) having addresses A.sub.WW, each WW consisting of W system words, with a location of each system word in a WW given by an offset (X), with each system word also identified by a system memory address, A.sub.SM, and with the system memory having a data I/O port and a control port, said data transfer apparatus also including a buffer memory having a data I/O port and a control port, where the system memory has an array of storage elements defined as sequentially addressed system word storage elements and with a selected subarray of storage elements embedded in the array defined by a starting address, an increment between rows (IBR) of the elements of the selected subarray and an increment between columns (IBC) of the elements of the selected subarray and a number of columns (NC), an improved system for transferring data from said selected subarray to said buffer during an SMEM read operation and from said buffer to said selected subarray during an SMEM write operation comprising:
- a system BUS (SBUS) including W word-segments, said system BUS coupled to the SMEM data I/O port so that the system words stored in the storage elements of a WW of said SMEM are transferred to corresponding word-segments of said SBUS during an SMEM read and so that the system words on said word-segments are transferred to corresponding storage elements in the WW during a SMEM write operation;
- a packing MUX for controllably coupling a selected word-segment of said SBUS to the I/O port of said buffer memory;
- a scattering DEMUX for controllably coupling the I/O port of said buffer memory to a selected word-segment of said SBUS;
- read control means, coupled to said SMEM, said packing MUX, and said buffer memory, for controlling said SMEM to transfer a subarray WW, being a WW including subarray system words stored in storage elements of said selected subarray, to said SBUS, with said subarray WW being on the SBUS for one WW cycle, for controlling said packing MUX to sequentially couple only the word-segments of the SBUS having subarray system words thereon to the data I/O port of the buffer memory during said WW cycle, and for sequentially writing the subarray system words transferred by said packing MUX to the I/O port of said buffer memory into selected storage locations in said buffer during said WW cycle;
- and
- write control means coupled to said SMEM, said scattering DEMUX, and said buffer memory for sequentially reading system words to be stored in the subarray storage elements from selected storage elements in said buffer memory, for controlling said scattering DEMUX to sequentially couple the I/O port of said buffer memory to only the subarray word-segments of SBUS corresponding to the subarray storage locatins of a given WW in said SMEM, and for sequentially writing each system word, transferred from said buffer memory to said subarray word-segments, into subarray storage locations of said given WW in said SMEM.
In a data transfer apparatus including a system memory (SMEM) having its storage elements organized into wide words (WW) having addresses A.sub.WW, each WW consisting of W system words, with a location of each system word in a WW given by an offset (X), with each system word also identified by a system memory address, A.sub.SM, with the system memory having a data I/O port and a control port, said data transfer apparatus also including a buffer memory having a data I/O port and a control port, and with the system memory having a block access mode and a random access mode, with the block access mode requiring a start address and a number of WWs in a block (PWCNT), and characterized by a block mode start-up time, BMS, and a block mode access time, BMAT, and with the random mode requiring an address and characterized by a random mode access time, RMAT, where BMAT is less than RMAT, where the system memory has an array of storage elements defined as sequentially addressed system word storage elements and with a selected subarray of storage elements embedded in the array defined by a starting address, an increment between rows (IBR) of the elements of the selected subarray and an increment between columns (IBC) of the elements of the selected subarray and a number of columns (NC), an improved system for transferring data from said selected subarray to said buffer during an SMEM read operation and from said buffer to said selected subarray during an SMEM write operation comprising:
- a system BUS (SBUS) including W word-segments, said system BUS coupled to the SMEM data I/O port so that the system words stored in the storage elements of a WW of said SMEM are transferred to corresponding word-segments of said SBUS during an SMEM read and so that the system words on said word-segments are transferred to corresponding storage elements in the WW during a SMEM write operation;
- a packing MUX for controllably coupling a selected word-segment of said SBUS to the I/O port of said buffer memory;
- a scattering DEMUX for controllably coupling the I/O port of said buffer memory to a selected word-segment of said SBUS;
- read control means, coupled to said SMEM, said packing MUX, and said buffer memory, for controlling said SMEM to transfer a subarray WW, being a WW including subarray system words stored in storage elements of said selected subarray, to said SBUS, with said subarray WW being on the SBUS for one WW cycle, for controlling said packing MUX to sequentially couple only the word-segments of the SBUS having subarray system words thereon to the data I/O port of the buffer memory during said WW cycle, and for sequentially writing the subarray system words transferred by said packing MUX to the I/O port of said buffer memory into selected storage locations in said buffer during said WW cycle;
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- write control means coupled to said SMEM, said scattering DEMUX, and said buffer memory for sequentially reading system words to be stored in the subarray storage elements from selected storage elements in said buffer memory, for controlling said scattering DEMUX to sequentially couple the I/O port of said buffer memory to only the subarray word-segments of SBUS corresponding to the subarray storage locations of a given WW in said SMEM, and for sequentially writing each system word, transferred from said buffer memory to said subarray word-segments, into subarray storage locations of said given WW in said SMEM with both read control means and write control means including:
- sequencer means for receiving parameters defining said subarray in said SMEM and for generating control signals to sequence block mode and random mode read operations to optimize a rate of transfer of the subarray system words of said subarray between said SMEM and said buffer;
- an SMEM controller for generating initialization and synchronization signals to control a read/write mode of said SMEM in response to SMEM control signals received from said sequencer means and for generating a data strobe signal when a word is transferred between the SMEM and the SBUS;
- a packer/scatterer controller for controlling said packing MUX and said scattering DEMUX in response to initialization, synchronization, and control signals from said sequencer means and SMEM controller;
- and
- a clock generator for generating a WWCLK signal, that defines WW cycles, and for generating an SWCLK signal, that defines system word cycles, with a SWCLK rate being a selected factor times a WWCLK rate.
Dependencies are inferred from the claim text.