US 4,839,801 AGranted

Architecture for block processing computer system

AssigneeSaxpy Computer Corporation

InventorsMark C. Nicely, Ronald Leavitt, Joel Mannion, Rob Schreiber, Gary R. Lang, Robert L. Papenberg, Joseph E. Straub

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Abstract

A block processing computing system includes a decomposition unit, a control circuit, a system memory, a data block path and a block processor. The decomposition unit receives externally-supplied primitive command packets and decomposes the primitive into machine language operations on computational blocks of data. The control circuitry generates control and address signals for performing the machine level operations. The data block path includes alignment circuitry for selecting data from burst-accessed blocks of data and a macropipeline for controllably storing and transferring blocks of data to and from the block processor. The block processor has interchangeable, double-buffered local zone memories and a parallel set of pipelined vector processors for performing block operations on computational blocks of data.

Claims32

Dependent claims

A computing system for performing externally-specified mathematical operations on externally-specified subarrays of an array of data words stored in a system memory (SMEM) having a memory I/O port, the system comprising:

(a) a system bus, said system bus being coupled to the memory I/O port for transmitting data words to and from the SMEM;
(b) alignment means, said alignment means being coupled to said system bus for controllably selecting data words from said system bus;
(c) block processing means for performing a block operation on at least one computational block of data words, said block processor means comprising a set of processors and block storage means for storing said at least one computational block of data words, said block processing means being coupled to said alignment means.
(d) decomposition and control means for receiving an externally-supplied command packet specifying the location of at least one subarray in said SMEM and specifying an operation to be performed on said at least one specified subarray, for defining computational blocks of data words from said at least one specififed subarray, for decomposing said operation into a series of block operations on said defined computational blocks, and for generating control and address signals to control and configure said SMEM to perform, at a burst transfer rate, at least one burst transfer of a plurality of data words onto said system bus, including the words contained in a first one of said defined computational blocks, and to control and configure said alignment means to select the words contained in said first defined computational block from said burst transferred plurality of data words on said system bus, and to control and configure said block processing means to transfer said selected words of said first defined computational block to selected storage locations of said block processing means, and to perform a first one of said series of block operations on said first defined computational block, said decomposition and control means being operatively coupled to said SMEM, said alignment means, and said block processing means.

1 more element

A computing system for performing externally-specified mathematic operations on externally-specified subarrays of an array of data words stored in a system memory (SMEM) having a memory I/O port, the system comprising:

(a) a system bus, said system bus being coupled to the memory I/O port for transmitting data words to and from the SMEM;
(b) a funnel buffer, said funnel buffer having first and second buffer I/O ports, for storing a computational block of data words of a specified subarray;
(c) alignment means, said alignment means being coupled to said system bus and to the first buffer I/O port of said funnel buffer, for controllably transferring selected data words between said system bus and selected storage locations of said funnel buffer;
(d) block processing means for performing a block operation on at least one computational block of data words, said block processing means including a plurality of processors and block storage means for storing said at least one computational block of data;
(e) switching means, said switching means being coupled to the second buffer I/O port of said funnel buffer and to the block processing means for controllably transferring selected data words between selected locations of said funnel buffer and said block processing means;
(f) block decomposition means for receiving an externally-supplied command packet specifying the locations of at least one subarray in the SMEM and specifying an operation to be performed on at least one specified subarray, for defining computational blocks of data words from said at least one specified subarray, for decomposing said operation into a series of block operations on said defined computational blocks, and for generating machine level operation signals (MLO fields) specifying machine-level operations to be performed on data words from said at least one specified subarray, said MLO fields including a data block definition set, a data block movement set and a data block computation set, said data block definition set for specifying said defined computational blocks of data words and for specifying the transfer of data words between the SMEM and said funnel buffer, said data block movement set for specifying the transfer of said defined computational blocks between said funnel buffer and said block processing means, and said data block computation set for specifying said series of block operations on said defined computational block of data words;
and
(g) control and address signal generating means comprising:
SMEM control and address signal generating means, said SMEM control and address signal generating means being coupled to said block decomposition means for receiving said MLO field data block definition set and coupled to the SMEM, to said alignment means, and to said funnel buffer, for generating, in response to said MLO field data block definition set, SMEM control and address signals to control and configure the SMEM to perform, at a burst transfer rate, a burst transfer of a plurality of data words onto said system bus, including the words in a first one of said defined computational blocks, and to control and configure said alignment means to select the words contained in said first defined computational block from said burst transferred words on the system bus, and to transfer said first defined computational block of words between said system bus and selected storage locations of said funnel buffer;
pipeline control and address signal generating means, said pipeline control and address signal generating means being coupled to said block decomposition means for receiving said MLO field data block movement set and coupled to said funnel buffer, said switching means, and to said block processing means, for generating, in response to said MLO field data block movement set, block movement control and address signals to control and configure said switching means and said block processing means to transfer said first defined computational block of words between selected locations of said funnel buffer and selected storage locations of said block processing means;
and
processor control and address signal generating means, said processor control and address signal generating means being coupled to said block decomposition means for receiving said MLO field data block computation set and coupled to said block processing means for generating, in response to said MLO field data block computation set, processor control and address signals to configure and control said block processing means to perform a first one of said series of block operations on said first defined computational block of words.

9 more elements

A method for performing externally-specified mathematical operations on externally specified subarrays of an array of data stored in a system memory (SMEM), said method comprising the steps of:

(a) receiving an externally-supplied command packet, said packet specifying the location of at least one subarray in the SMEM, specifying an operation to be performed on said at least one specified subarray, and specifying the desired location of a result subarray of data words;
(b) defining at least one computational block of data words from said at least one specified subarray;
(c) decomposing the specified operation into at least one block operation on said at least one defined computational block to produce at least one result block;
(d) designating the locations in said result subarray for storing the words in said at least one result block;
(e) generating control and address signals for moving data and performing said at least one block operation;
(f) in response to said control and address signals;
(i) performing a burst transfer of a plurality of data words from the SMEM onto a system bus (SBUS), said plurality of burst transferred data words including the words contained in a first one of said at least one defined computational blocks;
(ii) selecting the data words contained in said first defined computational block from the words on said SBUS;
(iii) transferring said selected words in said first defined computational block to selected storage locations in a block processor;
(iv) performing a first one of said series of block operations on said selected words in said first defined computational blocks to produce a first result block of data words;
and
(v) transferring the data words in said first result block to the designated locations in said result subarray.

9 more elements

Dependencies are inferred from the claim text.