US 4,815,113 A · Method for digital slope control of output signals of power amplifiers in semiconductor chips

Abstract

A method for the digital slope control of the output signals of power amplifiers, as well as a power amplifier suitable for carrying out the method as described. One way of representing the actual slope value is via the number of clock pulses applied to a counter during a measuring interval which depends in its duration on the slope. Such a measuring interval is produced by applying the pulses of a ring oscillator containing one of the power amplifiers to another counter until the overflow of the latter. Another mode of representing the actual slope value consists in counting the number of pulses of the ring oscillator during a measuring interval of predetermined duration. Actual and nominal values of the slope are compared. The results of this comparison change the contents of a left/right-shift register. Its parallel outputs influence, via control lines, control inputs of the power amplifiers in order to alter their slope by switching on or off output transistors arranged in parallel with respect to their switching paths.

Claims11

Dependent claims

A method for the digital slope control of output signals of power amplifiers of semiconductor chips, characterized by the following process steps:

representing a slope value of said signals via a number of clock pulses applied to a first counter during a measuring interval whose duration depends on the slope,
comparing in a comparator circuit the actual value represented by the count of said number of clock pulses with a nominal slope value stored in a nominal value register, and
applying the result of the comparison to a left/right-shift register whose parallel outputs connected to control inputs of said power amplifiers via which the slope of their output signals can be changed.

A circuit arrangement comprising:

a power amplifier having an output signal of a given slope value and control inputs,
a counter,
means for representing said given slope value of said output signal via a number of clock pulses applied to said counter during a measuring interval whose duration depends on said slope value,
a comparator circuit,
a first register having a nominal slope value stored therein,
means for comparing in said comparator circuit said number of clock pulses with the nominal slope value stored in said register,
a left/right-shift register having a plurality of parallel outputs,
means for applying the output of said comparator circuit to said left/right-shift register, and
means for coupling said plurality of parallel outputs to said control inputs of said power amplifier to modify the slope value of said output signal of said power amplifier.

6 more elements

Dependencies are inferred from the claim text.

Method for digital slope control of output signals of power amplifiers in semiconductor chips

Life of this patent

Method for digital slope control of output signals of power amplifiers in semiconductor chips

Life of this patent

Abstract

Claims11