Circuit and method for performing equal duty cycle odd value clock division and clock synchronization

A circuit for dividing a master clock signal having an approximately 50% duty cycle by an odd integer value defined by 2n+1 and producing an approximately 50% duty cycle output clock signal, comprising:

• a bistable multivibrator having two inputs and at least one output;
• means for setting said multivibrator to a first state for n counts of the master clock;
• means for clearing said multivibrator to a second state for n+1 counts of the master clock;
• and
• means for disabling said clearing means for 1/2 count of the master clock.

A circuit for providing a synchronized output clock signal derived by dividing down from one of a plurality of master clock signals having different frequencies, the output clock signal having a high and a low portion, and for providing an output clock signal wherein the rising edge of the clock signal immediately following a triggering event is limited to a prescribed interval, comprising:

• means for determining which of the plurality of master clocks is active;
• means for determining if the triggering event has occurred;
• means for determining the number of master clock cycles the low state of the output clock signal must be extended for synchronization based on which master clock is active and the occurrence of the triggering event;
• and
• means for extending the low state of the output clock signal and delaying the next rising edge of the output clock signal by the determined number of master clock cycles.

A circuit for providing asynchronized output clock signal derived from dividing one of a plurality of master clock signals having different frequencies and having approximately 50% duty cycles by an odd integer value to provide an approximately 50% duty cycle, synchronized output clock signal wherein the rising edge of the output clock signal immediately following a triggering event is limited to a prescribed interval, comprising:

• a bistable multivibrator having two inputs and at least one output;
• means for setting said multivibrator to a first state for n counts of the master clock;
• means for clearing said multivibrator to a second state for n+1 counts of the master clock;
• and
• means for disabling said clearing means for 1/2 count of the master clock;
• said means for setting and means for clearing comprising a state machine having set and clear output signals and having a plurality of states,
• one of said states enabling the rising edge of the output clock signal,
• one of said states enabling the falling edge of the output clock signal, and wherein
• the number of states occurring after said falling edge state and before said rising edge state varies depending on the active master clock frequency and the state at which the triggering event occurred

A method for dividing a master clock signal having an approximately 50% duty cycle by an odd integer value defined by 2n+1 and producing an approximately 50% duty cycle output clock signal, utilizing a bistable multivibrator having two inputs and at least one output, comprising:

• setting said multivibrator to a first state for n counts of the master clock;
• clearing said multivibrator to a second state for n+1 counts of the master clock;
• and
• disabling said clearing of said multivibrator for 1/2 count of the master clock.

A method for providing a synchronized output clock signal derived by dividing down from one of a plurality of master clock signals having different frequencies, the output clock signal having a high and a low portion, and for providing an output clock signal wherein the rising edge of the clock signal immediately following a triggering event is limited to a prescribed interval, comprising:

• determining which of the plurality of master clocks is active;
• determining if the triggering event has occurred;
• determining the number of master clock cycles the low state of the output clock signal must be extended for synchronization based on which master clock is active and the occurrence of the triggering event;
• and
• extending the low state of the output clock signal and delaying the next rising edge of the output clock signal by the determined number of master clock cycles.

A method for providing a synchronized output clock signal derived from dividing one of a plurality of master clock signals having different frequencies and having approximately 50% duty cycles by an odd integer value to provide an approximately 50% duty cycle, synchronized output clock signal wherein the rising edge of the output clock signal immediately following a triggering event is limited to a prescribed interval, and utilizing a bistable multivibrator having two inputs and at least one output, comprising:

• setting said multivibrator to a first state for n counts of the master clock;
• clearing said multivibrator to a second state for n+1 counts of the master clock;
• and
• disabling said clearing means for 1/2 count of the master clock;
• said setting step and said clearing step utilizing a state machine having set and clear output signals and having a plurality of states,
• enabling the rising edge of the output clock signal depending on one of said states,
• enabling the falling edge of the output clock signal depending on one of said states, and
• varying the number of states occurring after said falling edge state and before said rising edge state depending on the active master clock frequency and the state at which the triggering event occurred.