Chip separation and alignment apparatus

A chip separation and alignment apparatus comprising:

• (a) a principal chip storage chamber which, in use, contains a relatively large number of chips, said principal chip storage chamber having at least one air purge hole therein near the top thereof;
• (b) a secondary chip storage chamber which, in use, contains a relatively small number of chips, and secondary chip storage chamber being located beneath said principal chip storage chamber and being separated therefrom by a gate that defines the lower opening of a passageway sized and shaped to permit a small number of chips to pass abreast from said principal chip storage chamber to said secondary chip storage chamber;
• (c) first means for intermittently introducing blasts of pressurized air into said secondary chip storage chamber so as to scatteringly separate the chips in said secondary and primary chip storage chambers during alternating first periods, after which the chips fall back into the lower portions of said secondary and primary chip storage chambers under the force of gravity during alternating second periods;
• (d) a control plate having an upper surface, said control plate being disposed in said secondary chip storage chamber beneath the opening of said passageway into said secondary chip storage chamber and being sized, shaped, and positioned so that its upper surface supports a small number of chips during the alternating second periods and so that said control plate and said gate cooperate to prevent the chips from filling said secondary chip storage chamber during the alternating second periods;
• (e) a chip alignment hole projecting downwardly from said secondary chip storage chamber, said chip alignment hole being sized and shaped to pass the chips one after the other in linear array;
• and
• (f) second means for alternatingly blocking the lower end of said chip alignment hole and permitting one of the chips therein to exit said chip alignment hole and pass to a subsequent step.