Controllable delay circuit

A method utilizing a first and at least two additional amplifiers to provide a delayed output signal that changes state in adjustably delayed response to an input signal, said first and additional amplifiers having adjustable gains, the method comprising the steps of:

• delaying the input signal to produce at least two delayed signals, each delayed signal corresponding to a separate one of said additional amplifiers;
• amplifying said input signal using said first amplifier to produce a first amplifier output, said first amplifier having variable gain through a range of amplification;
• amplifying said delayed signals using their corresponding additional amplifiers to produce additional amplifier outputs, said additional amplifiers having variable gain through a range of amplification;
• combining said first and additional amplifier outputs to produce said delayed output signal;
• and
• adjusting a delay between a change in state in the input signal and a change in state in the output signal by adjusting the gain of at least one of the first and additional amplifiers.

A delay circuit for producing an output signal that changes state in delayed response to a change in state of an input signal, the delay circuit comprising:

• means for providing a plurality of delayed signals that change state at differeing times in delayed response to a change in state in the input signal;
• first amplification means for receiving the input signal as input and providing a first amplifier output, said first amplification means having variable gain through a range of amplification;
• a plurality of additional amplification means, each corresponding to a separate one of said plurality of delayed signals, each additional amplification means receiving its corresponding delayed signal as input and providing a separate additional amplifier output, said additional amplification means having variable gain through a range of amplification;
• and
• means for combining the first amplifier output and the additional amplifier outputs to provide the output signal.

A delay circuit for producing a delay circuit output signal that changes state in adjustably delayed response to a change in state of an input signal, the delay circuit comprising:

• means for providing a plurality of delayed signals that change state at differing times in delayed response to a change in state in the input signal;
• first amplification means having variable gain through a range of amplification for receiving the input signal as input and providing a first amplifier output;
• a plurality of additional amplification means, each having variable gain through a range of amplification, each corresponding to a separate one of said plurality of delayed signals, and each receiving its corresponding delayed signal as input and providing a separate additional amplifier output;
• means for controlling the gains of said first amplification means and said additional amplification means;
• and
• means for combining the first amplifier output and the additional amplifier outputs to provide the output signal.

A delay circuit responsive to a control signal for producing a delay circuit output signal that changes state in adjustably delayed response to a change in state of a delay circuit input signal, the delay circuit comprising:

• means for providing a plurality of delayed signals that change state at differing times in delayed response to a change in state in the delay circuit input signal;
• a first amplifier having a variable gain through a range of amplification controlled by a first gain control current applied thereto, for receiving the delay circuit input signal as input and providing a first differential current output, said first amplifier comprising:
• a first transistor having a first terminal, a second terminal, and a third terminal;
• and
• a second transistor having a first terminal, a second terminal, and a third terminal, the delay circuit input signal being applied across the first terminal of the first transistor and the first terminal of the second transistor, the second terminal of the first transistor being coupled to the second terminal of the second transistor and receiving said first gain control current, and the first differential current output being provided by the third terminal of the first transistor and the third terminal second transistor;
• a plurality of additional amplifiers each corresponding to a separate one of said plurality of delayed signals and each having a variable gain through a range of amplification controlled by a separate one of a plurality of additional gain control currents, each of said additional amplifiers receiving its corresponding delayed signal as input and providing a separate differential current additional amplifier output, each of said additional amplifiers comprising:
• a third transistor having a first terminal, a second terminal, and a third terminal;
• and
• a fourth transistor having a first terminal, a second terminal, and a third terminal, the corresponding delayed signal being applied across the first terminal of the third transistor and the first terminal of the fourth transistor, the second terminal of the third transistor being coupled to the second terminal of the fourth transistor and receiving one of said additional gain control currents, and the additional amplifier output signal being provided at the third terminal of the third transistor and the third terminal fourth transistor;
• means for supplying said first and additional gain control currents of adjustable magnitude to said first and additional amplifiers in accordance with a magnitude of said control signal;
• and
• means for combining the first amplifier output and the additional amplifier outputs to provide the output signal.