CMOS VLSI output driver with controlled rise and fall times
AssigneeRaytheon Company
InventorEdward T. Lewis
Life of this patent
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Abstract
A CMOS output driver having precise control of rise and fall times of signals generated from the output driver on a VLSI semiconductor chip. Two time-dependent voltage generators provide a separate ramp signal to each one of the gates of a CMOS inverter circuit. The ramp signal characteristics of each voltage generator are determined by the combination of a controlled current source charging a known capacitance.
Claims11
A CMOS output circuit for producing an output signal comprising:
- an input signal applied to said output circuit;
- first means coupled to receive said input signal for generating an approximately linear decreasing signal for control of said output signal rise time;
- second means coupled to receive said input signal for generating an approximately linear increasing signal for control of said output signal fall time;
- and means, free of any output feedback connections, for producing said output signal having a first input coupled to an output of said first control means and a second input coupled to an output of said second control means.
A driver circuit having an output signal with controlled rise and fall times comprising:
- an input signal applied to said driver circuit;
- a buffer circuit coupled to receive said input signal for providing drive capability for said input signal;
- a first voltage generator means coupled to an output of said buffer circuit for generating an approximately linear decreasing signal for signal rise time;
- a second voltage generator means coupled to said output of said buffer circuit for generating an approximately linear control of said output signal fall time;
- and
- complementary MOS transistors, free of any output feedback connections, having a first input coupled to an output of said first voltage generator and a second input coupled to an output of said second voltage generator for producing said output signal.
The method of controlling the rise and fall tims of an output signal from a VLSI chip output circuit comprsiing the steps of:
- providing an input signal to said output circuit;
- generating an approximately linear decreasing signal in response to one edge of said input signal with a first voltage generator means;
- generating an approximately linear increasing signal in response to the other edge of said input signal with a second voltage generator means;
- and
- producing said output signal having controlled rise and fall times with a pair of complementary MOS transistors, free of an output feedback connections, having a first input coupled to an output of said first voltage generator means and a second input coupled to an output of said second voltage generator means.
Dependencies are inferred from the claim text.