Gate turn-off thyristor
AssigneeMeidensha Corporation
InventorsYasuhide Hayashi, Kouki Matsuse, Yoshisuke Takita
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AssigneeMeidensha Corporation
InventorsYasuhide Hayashi, Kouki Matsuse, Yoshisuke Takita
Estimating the term…
In a gate turn-off thyristor including two separate gate electrodes, a first turn-off gate signal is applied to the first gate electrode and then a second turn-off gate signal is applied to the second gate electrode after a predetermined time has elapsed in order to improve the controllable anode current and to improve the capability against an anode-voltage rising rate. This is because the flow distribution of the anode current is unbalanced asymmetrical with respect to the structural center of the GTO and therefore the internal resistance between the cathode K and the second gate G.sub.2 is reduced, so that it is possible to increase the magnitude of the turn-off gate current near the time when the anode current drops sharply or at the end of the GTO switching off operation.
A gate turn-off thyristor having an anode electrode, a cathode electrode, first and second gate electrodes placed on the opposite sides of said cathode electrode, and a drive circuit for turning said thyristor on to cause an anode current flow through said anode electrode, said drive circuit including means for generating a first electrical signal to said first gate electrode and a second electrical signal to said second gate electrode after a substantial time delay relative to the first electrical signal for tuning said thyristor off to interrupt the anode current flow, said drive circuit means generating the first electrical signal to said first gate electrode to start a storage period and the second electrical signal to said second gate electrode to terminate the storage period a time after the second electrical signal is generated, said time being shorter than the substantial time delay, said drive circuit means including a signal generator for generating the first electrical signal to the first gate electrode, and a delay circuit coupled to said signal generator for converting the first electrical signal to the second electrical signal delayed relative to the first electrical signal.
The gate turn-off thyristor as claimed in calim 1, wherein said delay circuit includes means for sensing the anode current for generating a signal indicative of a sensed anode current level, and means responsive to the anode current level indicative signal for varying the substantial time delay.
The gate turn-off thyristor as claimed in calim 5, wherein said delay circuit includes means for increasing the substantial time delay as the sensed anode current level increases.
Dependencies are inferred from the claim text.