Self-aligned gate process

A process for producing a field effect semiconductor device in a body of semiconductor material, comprising the steps of:

• forming a region of first conductivity type extending into said body from a surface;
• applying a dielectric layer on said surface above said first region;
• applying a first layer of resist on said dielectric layer;
• patterning said first layer of resist to define a source implant area, a drain implant area and the location for a gate and removing the resist material in said defined locations to expose the surface of said dielectric layer in said defined locations;
• removing the dielectric material in said exposed areas to define on said surface of said body the locations for said gate, source implant area and drain implant area;
• removing said first resist;
• applying a second layer of resist, and patterning said second layer of resist to permit removal of said resist from said source implant area and said drain implant area;
• removing said second resist in said patterned areas to expose on said surface said source implant area and said drain implant area;
• subjecting said exposed areas to ion implantation to form a drain region and a source region in said body;
• removing said second resist;
• annealing said body to activate the implanted ions;
• and
• forming a gate on said surface in said gate defined location.