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US 4,791,610 AGranted
Semiconductor memory device formed of a SOI-type transistor and a capacitor
AssigneeFujitsu Limited
InventorYoshihiro Takemae
Life of this patent
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Abstract
A semiconductor memory (DRAM) device comprises memory cells, each of which is composed of an FET and a capacitor. The FET has an SOI structure. The capacitor is composed of a dielectric layer as an insulating layer for the SOI structure, an upper capacitor electrode as a semiconductor layer for the SOI structure, and a lower capacitor electrode as a semiconductor substrate. The substrate is biased with a voltage at an intermediate level between a first storage voltage and a second storage voltage.
Claims16
A semiconductor memory device comprising:
- a transistor formed in a semiconductor layer which is formed on an insulating layer, said insulating layer being formed on a well region formed in a semiconductor substrate, said semiconductor substrate being a first conductivity type, said well region being a second conductivity type opposite to said first conductitivy type, said transistor having a silicon on insulator structure where said silicon corresponds to said semiconductor layer and said insulator corresponds to said insulating layer;
- and
- a capacitor composed of a dielectric layer formed from said insulating layer, an upper capacitor electrode formed from said semiconductor layer, and a lower capacitor electrode formed from said well region wherein said dielectric layer is sandwiched between said upper and lower capacitor electrodes;
- the well region having a reverse bias to that of said substrate and being biased with a voltage at an intermediate level between a first storage voltage and a second storage voltage.
1 more element
A semiconductor memory device comprising:
- a semiconductor substrate of a first conductivity type;
- a well region of a second conductivity type, opposite said first conductivity type, disposed in a surface portion of said semiconductor substrate;
- an insulating layer composed of a first portion and a second portion and formed on said semiconductor substrate, said first portion being thinner than said second portion;
- a semiconductor layer formed on said insulating layer;
- a transistor formed in said semiconductor layer, said transistor having a silicon on insulator structure, where said silicon corresponds to said semiconductor layer and said insulator corresponds to said second portion of said insulating layer;
- a capacitor composed of a dielectric layer of said first portion of said insulating layer, an upper capacitor electrode formed from said semiconductor layer, and a lower capacitor electrode formed from said well portion wherein said dielectric layer is sandwiched between said upper capacitor electrode and said lower capacitor electrode;
- said well region having a reverse bias to that of said substrate, said well region being biased with an intermediate voltage between a first storage voltage and a second storage voltage.
4 more elements
Dependencies are inferred from the claim text.