Semiconductor integrated circuit device
AssigneeFujitsu Limited
InventorsYoshihide Sugiura, Hiroaki Ichikawa, Nobutake Matsumura, Nobuo Sasaki
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Abstract
A semiconductor integrated circuit device includes basic semiconductor elements arranged regularly in lines and rows and located at intersecting points of the lines and rows and wiring conductor layers arranged among the basic semiconductor elements regularly in lines and rows. In this semiconductor integrated circuit device, according to a desired logic operation, wiring conductor layers are cut or contact holes are formed on the wiring conductor layers to form wiring metal layers and connect the basic semiconductor elements to one another, so that an integrated circuit chip capable of performing the desired logic operation is obtained.
Claims14
A CMOS master slice array, comprising:
- a plurality of CMOS elements disposed in columns and rows;
- a plurality of first wiring patterns having a first length, disposed in parallel between adjacent ones of said CMOS elements within respective ones of said columns of said CMOS elements;
- a plurality of second wiring patterns having a second length, the second length being longer than the first length, disposed in parallel between adjacent ones of said columns of said CMOS elements and extending in a direction parallel to the columns;
- an insulating layer formed on said CMOS elements, said second wiring patterns, and said first wiring patterns, said insulating layer having a plurality of holes formed therein, and disposed above selected areas of said CMOS elements and said first and second wiring patterns;
- and
- a plurality of aluminum lines, selectively disposed above said plurality of holes and said insulating layer so as to provide desired electrical connections between the selected areas of said CMOS elements.
Dependencies are inferred from the claim text.