Dense vertical j-MOS transistor

Abstract

A j-MOS structure is disclosed which operates at high current densities and provides high current handling capability. A heavily doped N+ substrate, acting as a drain, has grown on it a lightly doped N- epitaxial layer. Within the epitaxial layer are multiple N+ buried regions, each within a corresponding P+ buried region, and bisecting each of the multiple N+ regions are vertical gates extending from the upper surface of the epitaxial layer down into the N+ substrate. These gates are insulated from the epitaxial layer and substrate via a thin gate oxide layer, but are electrically connected to the multiple N+ buried regions. Between each adjacent gate pair, N+ source regions are formed on the upper surface of the epitaxial layer. The gates are connected together via a conductive layer which also electrically shorts the gates to a poly-Si contact making contact with the N+ buried regions. The N+ source regions between the gates are also electrically connected together via the conductive layer, but are insulated from the gates and P+ and N+ buried regions.

Dependencies are inferred from the claim text.