Latch-up protection circuit for integrated circuits using complementary mos circuit technology

A latch-up protection circuit for use in integrated circuits using complementary MOS circuit technology, comprising:

• a semiconductor substrate;
• a well-shaped semiconductor zone of a first conductivity type located in said semiconductor substrate, said semiconductor substrate having a second conductivity type;
• a substrate bias terminal located in said well-shaped semiconductor zone;
• a substrate bias generator having an output connected to said substrate bias terminal;
• a capacitor having first and second capacitor surfaces, said first surface integrated in said well-shaped semiconductor zone in said semiconductor substrate;
• an electronic protection circuit connected to said substrate bias terminal and responsive to a voltage thereon, said electronic protection circuit connected to said second surface of said capacitor, said electronic protection circuit having at least one first field effect transistor with a predetermined threshold voltage, said second surface of said capacitor connected to a gate terminal of said first field effect transistor;
• and
• a capacitor bias generator for providing a predetermined voltage connected to said electronic protection circuit, said electronic protection circuit connecting said capacitor bias generator to said second surface of said capacitor when a voltage on the substrate bias terminal is less than a sum of a reference potential and the threshold voltage of said first transistor in said electronic protection circuit, and said electronic protection circuit disconnecting said capacitor bias generator from said second surface of said capacitor when a voltage on the substrate bias terminal is greater than said sum.

A latch-up protection circuit for use in integrated circuits using complementary MOS circuit technology, comprising:

• a semiconductor substrate having a substrate bias terminal contained thereon;
• a substrate bias generator having an output connected to said substrate bias terminal;
• a capacitor having first and second capacitor surfaces, said first surface integrated in said semiconductor substrate;
• an electronic protection circuit having a first input connected to said substrate bias terminal and a second input connected to a reference potential, having load element with a first terminal connected to a predetermined positive supply voltage, and having at least a first field effect transistor with a first terminal connected to said second input, a gate terminal connected to said first input, a substrate terminal connected to said output of said substrate bias generator and a second terminal connected to a second terminal of said load element, said first field effect transistor having a predetermined threshold voltage;
• a third field effect transistor having a gate connected to said second terminal of said load element, having a substrate terminal connected to said output of said substrate bias generator, a source connected to said second surface of said capacitor and a drain;
• and
• a capacitor bias generator for providing a predetermined voltage connected to said drain of said third field effect transistor in said electronic protection circuit, said electronic protection circuit connecting said capacitor bias generator to said second surface of said capacitor when a voltage on the substrate bias terminal is less than a sum of a reference potential and said threshold voltage of said first transistor in said electronic protection circuit, and said electronic protection circuit disconnecting said capacitor bias generator from said second surface of said capacitor when a voltage on said substrate bias terminal is greater than said sum.