US 4,791,316 A · Latch-up protection circuit for integrated circuits using complementary MOS circuit technology

Abstract

A latch-up protection circuit for an integrated circuit using complementary MOS circuit technology has a substrate bias generator that applies a negative substrate bias to a semiconductor substrate having a p-conductive material into which a well-shaped semiconductor zone of n-conductive material is inserted. In order to avoid latch-up effects in the integrated circuit, an electronic protection circuit interrupts the capacitive charging currents of a capacitor in the substrate depending on the potential of the semiconductor substrate which is taken at a doped substrate bias terminal. The electronic protection circuit disconnects a capacitor bias generator from the capacitor when a voltage on the substrate bias terminal is greater than a difference between a reference potential and a threshold voltage of a first transistor in the electronic protection circuit. The electronic protection circuit connects the capacitive bias generator to the capacitor when a voltage on the substrate bias terminal is lower than the difference. No quiescent current flows through the electronic protection circuit during normal operation of the integrated circuit.

Claims21

Dependent claims

A latch-up protection circuit for use in integrated circuits using complementary MOS circuit technology, the integrated circuit having a substrate bias terminal and a doped semiconductor substrate, the substrate biased terminal connected to an output of a substrate bias generator, comprising:

a capacitor having first and second capacitor surfaces, said first surface integrated in the semiconductor substrate;
an electronic protection circuit connected to the substrate biased terminal and controlled by a voltage thereon, said electronic protection circuit also connected to said second surface of said capacitor, said electronic protection circuit having at least a first transistor with a predetermined threshold voltage;
and
a capacitor bias generator for providing a predetermined voltage connected to said electronic protection circuit, said electronic protection circuit disconnecting said capacitor bias generator from said second surface of said capacitor when a voltage on the substrate bias terminal is greater than a difference between a reference potential and said threshold voltage of said first transistor in said electronic protection circuit, and said electronic protection circuit connecting said capacitor bias generator to said second surface of said capacitor when a voltage on the substrate bias terminal is less than said difference.

1 more element

A latch-up protection circuit for use in integrated circuits using complementary MOS circuit technology, the integrated circuit having a substrate bias terminal in a doped semiconductor substrate, the substrate bias terminal connected to an output of a substrate bias generator, comprising:

a capacitor having first and second capacitor surfaces, said first surface integrated in the semiconductor substrate;
an electronic protection circuit having a first input connected to the substrate bias terminal and a second input connected to a reference potential, having a load element with a first terminal connected to a predetermined positive supply voltage, having at least a first field effect transistor with a first terminal and a substrate terminal connected to said first input, a gate terminal connected to said second input and a second terminal connected to a second terminal of said load element, said load element and said first field effect transistor thereby being in series, and having a p-channel field effect transistor with a gate connected to said second terminal of said load element, a substrate terminal connected to said positive supply voltage, a drain connected to said second surface of said capacitor and a source terminal, said first field effect transistor having a predetermined threshold voltage;
and
a capacitor bias generator for providing a predetermined voltage connected to said source terminal of said p-channel field effect transistor in said electronic protection circuit, said electronic protection circuit disconnecting said capacitor bias generator from said second surface of said capacitor when a voltage on the substrate bias terminal is greater than a difference between said reference potential and said threshold voltage of said first field effect transistor, and said electronic protection circuit connecting said capacitor bias generator to said second surface of said capacitor when the voltage on the substrate bias terminal is less than said difference.

1 more element

a capacitor having first and second capacitor surfaces, said first surface integrated in the doped semiconductor substrate;
an electronic protection circuit having a first input connected to the substrate bias terminal and a second input connected to a reference potential, having a load element with a first terminal connected to a predetermined positive supply voltage, having at least a first field effect transistor with a first terminal and a substrate terminal connected to said first input, a gate terminal connected to said second input, and a second terminal connected to a second terminal of said load element, said load element and said first field effect transistor thereby being in series and said first field effect transistor having a predetermined threshold voltage;
an inverter having an input connected to said second terminal of said load element and having an output;
an n-channel field effect transistor having a gate connected to said output of said inverter, a substrate terminal connected to the output of the substrate bias generator, a source connected to said second surface of said capacitor and a drain;
and
a capacitor bias generator for providing a predetermined voltage connected to said drain of said n-channel field effect transistor in said electronic protection circuit, said electronic protection circuit disconnecting said capacitor bias generator from said second surface of said capacitor when a voltage on the substrate bias terminal is greater than a difference between said reference potential and said threshold voltage of said first field effect transistor, and said electronic protection circuit connecting said capacitor bias generator to said second surface of said capacitor when a voltage on the substrate bias terminal is lower than said diference.

3 more elements

Dependencies are inferred from the claim text.

Latch-up protection circuit for integrated circuits using complementary MOS circuit technology

Life of this patent

Latch-up protection circuit for integrated circuits using complementary MOS circuit technology

Life of this patent

Abstract

Claims21