Integrated circuit structure having gate electrode and underlying oxide and method of making same
AssigneeAdvanced Micro Devices, Inc.
InventorsWilliam P. Cox, Mong-Song Liang
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Abstract
An improved electrically erasable programmable read only memory (EEPROM) integrated circuit structure and method for its fabrication is disclosed, having an enhanced interface between the floating gate electrode and the underlying tunnel oxide. The structure is capable of a relatively higher floating gate breakdown voltage and is less subject to charge migration from the floating gate and resultant charge trapping in the tunnel oxide. The improvements comprise forming the floating gate electrode from amorphous silicon and doping the silicon floating gate by implantation with a dopant, such as arsenic or phosphorus, under conditions wherein the doping agent will not easily migrate into the underlying tunnel oxide layer.
Claims36
An improved MOS type integrated circuit structure, having a gate electrode over a gate oxide, wherein said gate electrode comprises an amorphous silicon material.
An improved integrated circuit structure, wherein a gate electrode formed over a gate oxide in an MOS type device comprises a silicon material doped with a doping agent to enhance the conductivity of said silicon material such that migration of said doping agent into adjoining oxide layers is inhibited.
An improved integrated circuit structure wherein the gate electrode formed over the gate oxide in an MOS type device is formed from amorphous silicon.
An improved integrated circuit structure wherein a gate electrode formed over a gate oxide in an MOS type device comprises a silicon material which is doped by implantation of a doping agent to enhance the conductivity of said silicon material under conditions which will inhibit migration of the doping agent into adjoining oxide layers.
A method of constructing an EEPROM device having an improved breakdown voltage across a gate oxide therein which comprises:
- forming a floating gate electrode from amorphous silicon to provide an enhanced interface between said floating gate electrode and said gate oxide to thereby increase the breakdown voltage of said gate oxide.
A method of constructing an improved integrated circuit structure having a higher breakdown voltage across a gate oxide therein which comprises forming over said gate oxide a gate electrode from an amorphous silicon material to form a more uniform interface between said gate electrode and said gate oxide.
An improved method of constructing an EEPROM device characterized by:
- forming a floating gate over a tunnel oxide layer using a material which will form a relatively smooth interface with the underlying tunnel oxide to provide an improved breakdown voltage of said tunnel oxide.
Dependencies are inferred from the claim text.